Pre-conditioner for measuring high-speed time intervals over a low-bandwidth path

A pre-conditioner for conveying timing relationships of signals over a bandwidth-limited pathway between a unit under test (UUT) and a measurement instrument, comprising:

• first and second input nodes for receiving at least one input signal from the UUT;
• first and second output nodes for respectively providing first and second output signals to the measurement instrument;
• a first circuit branch including a first frequency divider having an input coupled to the first input node and an output coupled to the first output node;
• a second circuit branch including a second frequency divider having an input coupled to the second input node and an output selectably coupled to the second output node;
• and
• a clocked memory device having a first input coupled to the output of one of the first and second frequency dividers, a second input coupled to the input of the second frequency divider, and an output selectably coupled the second output node.

A tester for determining whether a unit under test (UUT) is operating properly, comprising:

• a plurality of channels connectable to the UUT and each including at least one voltage comparator;
• a measurement instrument for measuring timing characteristics of the UUT;
• and
• a signal pathway conveying timing signals from the plurality of channels to the measurement instrument,
• wherein each of the plurality of channels further includes a pre-conditioner for conveying timing signals between the at least one comparator and the measurement instrument via the signal pathway, the pre-conditioner comprising
• first and second input nodes for receiving at least one signal from the UUT;
• first and second output nodes for respectively providing first and second output signals to the measurement instrument;
• a first circuit branch including a first frequency divider having an input coupled to the first input node and an output coupled to the first output node;
• a second circuit branch including a second frequency divider having an input coupled to the second input node and an output selectably coupled to the second output node;
• and
• a clocked memory device having a first input coupled to the output of one of the first and second frequency dividers, a second input coupled to the input of the second frequency divider, and an output selectably coupled the second output node.

In an electronic test system, a method for accurately measuring time intervals between first and second timing events at a unit under test (UUT) over a bandwidth-limited pathway, comprising:

• (a) dividing the frequency of the first timing events to generate a first frequency-divided signal, the first frequency-divided signal having a first edge coincident with an initial first timing event and subsequent edges of the same polarity as the first edge coincident with every Nth first timing event thereafter;
• (b) generating a second frequency-divided signal having edges coincident with second timing events and changing state at most once for each change of state of the first frequency-divided signal only after the first frequency-divided signal changes state;
• (c) conveying the first and second frequency-divided signals a measurement instrument;
• and
• (d) determining the time interval between the first and second timing events by measuring a time interval between the first and second frequency-divided signals.