Built-in self test for content addressable memory

A computer system comprising:

• at least one processor that executes instructions;
• content addressable memory (CAM) structure that has a plurality of entries each having N number of bits, wherein N is greater than 1 and wherein said CAM structure is accessible by said processor to satisfy memory access requests;
• said CAM structure comprising built-in circuitry for testing the integrity of said CAM structure, wherein said built-in circuitry does not require circuitry for reading memory data out of said CAM to test the integrity of said CAM structure;
• said built-in circuitry comprising
• (a) logic for storing a first value to each of said plurality of entries of said CAM structure,
• (b) logic that generates at least N test values, wherein each of said N test values has one bit that is different from a corresponding bit of said first value, and
• (c) compare circuitry operable to compare each of said generated N test values with said entries, wherein for each of said generated N test values said compare circuitry compares bits of the test value with corresponding bits of each of said plurality of entries in parallel to determine in parallel for said plurality of entries whether the test value matches any of said plurality of entries.

An integrated circuit comprising:

• content addressable memory (CAM) structure that has a plurality of entries each having N number of bits, wherein N is greater than 1;
• and
• means for testing tie integrity of said CAM structure, wherein said testing means does not require a means for reading memory data out of said CAM structure and wherein said testing means comprises
• means for storing a first value to each of said plurality of entries,
• means for generating at least N test values, wherein each of said N test values has one bit that is different from a corresponding bit of said first value, and
• means, operable for each of said generated N test values, for comparing bits of the test value with corresponding bits of each of said plurality of entries in parallel.