Detecting interport faults in multiport static memories

A method of checking for interport faults in a multiport static random access memory device, comprising:

• consecutively addressing a plurality of memory cells through a first port;
• performing for each address two memory write operations in parallel, including a first write and a second write, wherein the first write occurs through said first port, and the second write occurs through a second port at a fixed number of cells consecutively behind the first write;
• and
• verifying the result of the first write.

A memory testing circuit capable of interfacing a multiport memory device, comprising:

• a test address register configured to provide a first memory address to a first memory port;
• a concurrent address register configured to provide a second memory address to a second memory port;
• a data register configured to store data for memory read and write cycles on a plurality of memory ports;
• and
• a control logic capable of executing memory operations over multiple ports concurrently through said test address register, said concurrent register, and said data register;
• wherein said control logic is configured to consecutively access a plurality of memory addresses through said test address register to perform a first set of concurrent operations, including:
• a first memory operation executed through said first port at a memory address defined by the value of said test address register;
• and
• a second memory operation executed through said second port at a memory address defined by the value of said concurrent address register, wherein the second memory operation occurs concurrently with the first memory operation and at an address corresponding to a fixed number of cells consecutively behind the first memory operation.

A multiport memory device, comprising:

• an array of memory cells having multiple ports;
• an input/output interface coupled to said array of memory cells, said interface including address and data signals;
• a built in self test unit coupled to said array via said input/output interface and configured to check for interport faults in said array, said built in self test unit comprising:
• a first address register that provides a first address value to said interface;
• a second address register that provides a second address value to said interface;
• a data register that stores data for read and write operations in said array;
• and
• a control logic device that controls the operation of said first address register, said second address register, and said data register;
• wherein said built in self test circuit performs a series of test memory operations at each of a plurality of addresses in said memory array through a first of said multiple ports;
• wherein said built in self test circuit performs a concurrent memory operation through a second port of said memory array during each test memory operation, and wherein said concurrent memory operations occur at a fixed number of addresses away from the test memory operations.