On-line testing of the programmable logic blocks in field programmable gate arrays

Abstract

A method of self-testing the programmable logic blocks of field programmable gate arrays (FPGAs) during normal on-line operation includes configuring the FPGA into an initial self-testing area and a working area. The self-testing area may be further subdivided into self-testing tiles for concurrent testing if desired. The programmable logic blocks located within the self-testing area or self-testing tiles are established to function as a test pattern generator, an output response analyzer, and equivalently configured programmable logic blocks under test for testing. An exhaustive set of test patterns generated by the test pattern generator are applied to the programmable logic blocks under test which are repeatedly reconfigured in order to completely test the programmable logic blocks in all possible modes of operation. The outputs of the logic blocks are compared by the output response analyzer and resultant fault status data for each programmable logic block under test is received by a controller in communication with a memory for storing usage and fault status data for each programmable logic block. After testing each logic block in the initial self-testing area, the FPGA is reconfigured such that a portion of the working area becomes a subsequent self-testing area and at least a portion of the initial self-testing area replaces that portion of the working area. In other words, the self-testing area roves around the FPGA repeating the steps of testing and reconfiguring the programmable logic blocks until the entire FPGA has undergone testing or continuously.

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