Testing system and methods with protocol pattern injection and external verification
AssigneeEMC Corporation
InventorsBrian K. Bailey, Robert D. Maiorana, Douglas Peeke
Life of this patent
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Abstract
A system and method of testing processor boards in which a test path is created by setting switches in distribution hubs and the devices under test. Test signals are sent through the test path and errors in the signals are used to identify faulty boards. The distribution hubs of an embodiment can detect, report and eliminate errors in the test signals. A command path from a host to the distribution hubs and devices under test is provided through a multi-terminal connector. The command path is preferably separate from the test path. A test signal generator may be included. The system may be particularly adapted for fiber channel testing.
Claims37
A test system comprising:
- at least one distribution hub, each having a plurality of ports for connecting to devices under test;
- a test signal generator connected in series with said at least one distribution hub;
- and
- a host for creating a test path by setting switches in said at least one distribution hub and in the devices under test and causing said test signal generator to send test signals along the test path.
A fibre channel test system comprising:
- at least one distribution hub, each having a plurality of ports for connecting to devices under test;
- a host for creating a test path by setting switches in said at least one distribution hub and in the devices under test and causing fibre channel protocol signals which do not target a device under test to be sent along the test path;
- and
- wherein said at least one distribution hub detects and reports errors in the fibre channel protocol signals to help locate a faulty device.
A test system comprising:
- at least one distribution hub, each having a plurality of ports for connecting to devices under test;
- a multi-terminal connector providing a command path to each of said at least one distribution hub and each of the devices under test;
- a host connected to the command path of said multi-terminal connector for setting switches in said at least one distribution hub and in the devices under test, the switches thereby creating a test path independent of the command path and said host including means for causing test signals to be sent along the test path.
A fibre channel test system comprising:
- a first fibre channel signal generator;
- a second fibre channel signal generator;
- a first at least one distribution hub having a plurality of ports, said first at least one hub being connected in series with said first fiber channel signal generator;
- a second at least one distribution hub having a plurality of ports, said second at least one hub being connected in series with said second fiber channel signal generator and wherein dual ported devices under test are connected to said first at least one distribution hub and to said second at least one distribution hub;
- and
- a host for creating a first test loop by setting switches in said first at least one distribution hub and in the devices under test and a second test loop by setting switches in said second at least one distribution hub and in the devices under test and causing said first and second fibre channel signal generators to send test signals along their respective test paths.
A method of testing a plurality of processor boards comprising:
- connecting the plurality of processor boards to at least one distribution hub;
- communicating with the plurality of processor boards and the at least one distribution hub through a command path to set switches therein to create a test path separate from the command path;
- generating test signals;
- sending the test signals through the at least one distribution hub into one or more of the processor boards along the test path;
- and
- identifying a processor board that causes an error in said test signals.
A method of testing a plurality of fibre channel boards comprising:
- connecting the plurality of fibre channel boards to at least one distribution hub;
- setting switches in the plurality of fibre channel boards and in the at least one distribution hub to create a test loop;
- generating fibre channel protocol test signals which do not target any of the fibre channel boards so as to loopback through the test loop;
- sending the test signals through the test loop;
- and
- detecting in one of the at least one distribution hub an error in the test signals to locate a faulty fibre channel processor board.
Dependencies are inferred from the claim text.