Array VT mode implementation for a simultaneous operation flash memory device
AssigneesAdvanced Micro Devices, Inc., Fujitsu Limited
InventorsTakao Akaogi, Tiao-Hua Kuo, Fan W. Lai
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Abstract
An array threshold voltage test mode for a flash memory device is disclosed. During the test mode, a test voltage is routed directly to the gates of the flash memory transistors selected by a given address. If the test voltage causes the selected transistors to change state by crossing their threshold voltage level, the change will be reflected in the data outputs of the device. By varying the test voltages and the addresses and monitoring the data outputs, the array threshold voltage distribution can be determined for the entire device.
Claims30
A method for determining the transistor threshold voltage distribution in a flash memory array of a flash memory chip, said memory array comprising a first memory bank and a second memory bank, the method comprising:
- (a) selecting a first memory cell within said first memory bank, said first memory cell comprising a gate input;
- (b) placing a voltage on said gate input;
- (c) determining whether said first memory cell changes state after (b) while simultaneously placing a voltage on a second memory cell in said second memory bank;
- and
- (d) changing said voltage on said first memory cell based on (c).
An apparatus for determining a transistor array voltage threshold distribution, said apparatus comprising:
- a flash memory array comprising a first memory bank and a second memory bank, said first memory bank comprising a first flash memory transistor, said flash memory transistor comprising a gate input and a drain output;
- a variable voltage source operative to produce a voltage at said gate input;
- an address decoder coupled with said flash memory array for selecting said first flash memory transistor;
- a voltage inducer coupled with said flash memory array, said variable voltage source and said address decoder and operative to induce said voltage on said gate input of said selected first flash memory transistor;
- a comparator coupled with said drain output and operative to determine a state of said first flash memory transistor;
- a first multiplexer coupled to said first memory bank and to said second memory bank;
- and, a second multiplexer coupled to said first memory bank and to said second memory bank.
An apparatus for determining the transistor turn on threshold voltage distribution for a flash memory device, said apparatus comprising:
- a first memory bank comprising a memory cell transistor, said memory cell transistor comprising a gate input and defined by a threshold voltage (Vt) and operative to store a data value;
- a second memory bank;
- a first multiplexer coupled to said first memory bank and to said second memory bank;
- and,
- a second multiplexer coupled to said first memory bank and to said second memory bank.
- a test voltage source for providing a test voltage to said gate input of said memory cell transistor;
- a read voltage source for providing a read voltage to said gate input of said memory cell transistor;
- a selector coupled with said test voltage source and said read voltage source for selecting between said test voltage source and said read voltage source and having an output for a selected voltage;
- an address decoder coupled with said memory bank and said selector and operative to select said memory cell transistor and provide said selected voltage to said gate input;
- a read circuit operative to read the output of said selected memory cell transistor and whether said selected voltage is greater than said Vt and further operative to output a logical 1 if said selected voltage is greater than said Vt and a logical zero if said selected voltage is less than said Vt;
- and
- wherein said flash memory device operates in a test mode where said selector selects said test voltage source and a normal mode where said selector selects said read voltage source.
A method for determining the transistor threshold voltage distribution in a flash memory array of a flash memory chip, said memory array comprising a first memory bank and a second memory bank, the method comprising:
- (a) selecting a first memory cell within said first memory bank, said first memory cell comprising a gate input;
- (b) placing a voltage on said gate input;
- and
- (c) determining whether said first memory cell changes state after (b) while simultaneously programming a memory cell in said second memory bank.
Dependencies are inferred from the claim text.