On-the-fly memory testing and automatic generation of bitmaps
AssigneeHewlett-Packard Development Company, L.P.
InventorsJeffery C. Brauch, Jay E. Fleischman
Life of this patent
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Abstract
A method and apparatus for locating defects in an on-chip memory of an integrated circuit is presented. During a memory test of on-chip memory, a known data value is written to a word in the on-chip memory, and an output data value is read back from the same addressed word in memory. A comparison of the output data value and expected data value is performed within the integrated circuit, producing a comparison result indicating which of the bit cells in the addressed word have failed. The address and comparison result are transferred external to said integrated circuit and correspond to a bitmap entry in a bitmap. The execution of a full memory test results in a complete bitmap indicating all the failed cells of the on-chip memory.
Claims23
An apparatus for locating defects in an on-chip memory of an integrated circuit, comprising:
- an on-chip address generator which generates an address and stores said address in an address register;
- an on-chip data generator which generates an expected data value and stores said expected data value in an expected data register;
- an on-chip processor which writes said expected data value from said expected data register to said address indicated in said address register in said on-chip memory and reads an output data value from said address indicated in said address register in said on-chip memory;
- and
- an on-chip fault detector operable to compare said output data value and said expected data value indicated in said expected data register, to generate a bitwise comparison result indicating which, if any, of a plurality of bit cells at said address have failed, and if any of said plurality of bit cells at said address have failed, to store said bitwise comparison result in a compare result register for retrieval by an external source.
An apparatus for locating defects in an on-chip memory of an integrated circuit, comprising:
- an address register for storing an address, generated in said integrated circuit, of a word in said memory, said word comprising a plurality of bit cells;
- an expected data register for storing an expected data value generated in said integrated circuit and written to said word in said memory;
- an on-chip comparator operable to receive an output data value read from said word in said memory, and to compare said output data value and said expected data value to generate a comparison result indicating which of said plurality of bit cells in said word have failed;
- and
- a compare result register for storing said comparison result generated by said on-chip comparator for retrieval by an external source.
A method for locating defects in an on-chip memory of an integrated circuit, comprising:
- generating in said integrated circuit an address in said on-chip memory;
- storing said address in an address register;
- generating in said integrated circuit an expected data value;
- storing said expected data value in an expected data register;
- writing said expected data value indicated in said expected data register to said address in said on-chip memory;
- reading an output data value from said address indicated in said address register in said on-chip memory;
- performing an on-chip comparison of said output data value and said expected data value indicated in said expected data register;
- and
- producing a bitwise comparison result indicating which, if any, of a plurality of bit cells at said address indicated in said expected data register have failed;
- and
- if any of said plurality of bit cells at said address indicated in said expected data register have failed, storing said bitwise comparison result in a compare results register for retrieval by an external source.
Dependencies are inferred from the claim text.