Hierarchical JTAG based checkstop architecture for computer systems

Abstract

A checkstop architecture allows an entire computer system to be immediately halted when a failure(s) or error(s) has occurred at a chip, component, device, sub-system, etc. The present checkstop architecture provides a way of preserving and later providing the state of the computer system at failure or error. The checkstop architecture utilizes a single-wire checkstop that provides a way for quickly stopping all chips in the system and a JTAG that provides a way for querying the error registers in determining which chip pulled checkstop first and what had occurred to cause the error. The present system and method also utilizes a service processor, various computer devices, and at least one central checkstop collection location. The occurrence of the checkstop at one of the computer devices is detected by its internal checkstop operation. The occurrence of the checkstop is driven to the at least one central checkstop collection location, all other of the computer devices, and the service processor. A single-wire checkstop provides a way for all chips of the entire computer system to be halted when the occurrence of the checkstop has been detected. Error registers of the chips are then queried via a separate JTAG to identify the chip which first pulled checkstop and what caused the error. The service processor captures the state of the entire computer system at the time of checkstop occurrence and determines the initial source of the checkstop by tracing back from the central checkstop collection chip.

Dependencies are inferred from the claim text.