Scalable virtual timer architecture for efficiently implementing multiple hardware timers with minimal silicon overhead

A scalable virtual timer system, comprising:

• a free running counter having a readable state;
• a plurality of period registers, each period register of the plurality of period registers storing a sum of an initial state of the free running counter and a desired count duration for a virtual timer of a plurality of virtual timers associated with the period register;
• and
• a plurality of comparators, each comparator of the plurality of comparators triggering a terminal count for a virtual timer of the plurality of virtual timers associated with the comparator when a current state of the free running counter matches the sum of a desired count duration for a virtual timer and an initial state of the free running counter stored in a period register associated with the virtual timer.

A microcontroller, comprising:

• an execution unit;
• and
• a scalable virtual timer subsystem coupled to the processor, comprising:
• a free running counter having a readable state;
• and
• a content addressable memory for storing a sum of an initial state of the free running counter and a desired count duration for a virtual timer for each virtual timer of a plurality of virtual timers, the content addressable memory generating a terminal count when a current state of the free running counter matches the sum of an initial state of the free running counter and a desired count duration for the virtual timer stored in the content addressable memory, the initial state being a state of the free running counter when the virtual timer initiates counting.

A microcontroller, comprising:

• an execution unit;
• and
• a scalable virtual timer subsystem coupled to the execution unit, comprising:
• a free running counter readable by the execution unit, the execution unit adding a desired count duration for a virtual timer of a plurality of virtual timers to an initial state of the free running counter, the initial state being a state of the free running counter when the virtual timer initiates counting;
• a plurality of period registers, each period register of the plurality of period registers storing a sum of an initial state of the free running counter provided by the execution unit and a desired count duration for a virtual timer of the plurality of virtual timers associated with the period register;
• and
• a plurality of comparators, each comparator of the plurality of comparators triggering a terminal count for a virtual timer of the plurality of virtual timers associated with the comparator when a current state of the free running counter matches the sum of an initial state of the free running counter and a desired count duration stored in the period register associated with the virtual timer.

A method of efficiently implementing multiple hardware timers with minimal silicon overhead using a scalable virtual timer system, the scalable virtual timer system including a free running counter, a plurality of virtual timers, and a storing means having a plurality of portions associated with the plurality of virtual timers, the method comprising the steps of:

• storing a sum of an initial state of the free running counter and a desired count duration for a virtual timer of the plurality of virtual timers to a portion of the storing means associated with the virtual timer;
• reading current states of the free running counter;
• detecting when a current state of the free running counter matches the sum of an initial state of the free running counter and a desired count duration for a virtual timer of the plurality of virtual timers stored in a portion of the storing means associated with the virtual timer;
• and
• generating a terminal count in response to detection of a match by the detecting step.