Data processing system and image processing system

A data processor formed on a semiconductor chip used with a synchronous DRAM, the synchronous DRAM having a mode register, receiving a first clock signal, inputting address data and a control signal and outputting data in synchronism with the first clock signal, the data processor comprising:

• a clock driver;
• and
• a control unit coupled to the clock driver,
• wherein the clock driver is received a second clock signal generated from an external clock generator, and outputs the first clock signal,
• wherein the control unit generates a command for the synchronous DRAM and can output a chip select signal, a column address signal, a row address strobe signal and a write enable signal, and
• wherein the control unit outputs a mode information to address terminals of the synchronous DRAM.