Memory clock generator and method therefor

A memory clock generator comprising:

• a shift register operable for inputting a first input signal in response to a first clock signal, said shift register having a predetermined first set of output taps;
• first logic circuitry operable for receiving signals from said first set of output taps and a plurality of control signals operable for selecting a ratio of a period of said memory clock to a period of said first clock, wherein said first logic circuitry outputs a second clock signal, said memory clock being output in response to said second clock signal;
• wherein said first logic circuitry comprises:
• a plurality of AND gates, each AND gate having first and second inputs and an output, each first input operable for receiving a signal from one of said first set of output taps, and each second input being operable for receiving a corresponding one of said plurality of control signals;
• and
• an OR gate having a plurality of inputs, each AND gate output being coupled to one of said plurality of OR gate inputs, and one of said plurality of OR gate inputs being coupled to a corresponding one of said first set of output taps, said OR gate outputting said second clock signal.

A method of generating a memory clock comprising the steps of:

• shifting a first input pulse through a shift register;
• tapping a first predetermined set of outputs off of said shift register;
• logically combining said first set of outputs with a first plurality of first control signals, wherein said first plurality of first control signals are operable for selecting a ratio of a period of said memory clock to a period of said first clock signal;
• and
• outputting a result of said step of logically combining said first set of outputs, said memory clock being generated in response to said result;
• wherein said shift register comprises a plurality of latch pairs.

A data processing system comprising:

• a central processing unit (CPLJ), said CPU including a memory clock generator;
• and
• a memory operable for storing data and instructions for said CPU, wherein said memory communicates said data and instructions in response to a memory clock from said memory clock generator, said memory clock generator comprising:
• a shift register operable for inputting a first input signal in response to a first clock signal, said shift register having a predetermined first set of output taps;
• and
• first logic circuitry operable for receiving signals from said first set of output taps and a plurality of control signals operable for selecting a ratio of a period of said memory clock to a period of said first clock, wherein said first logic circuitry outputs a second clock signal, said memory clock being output in response to said second clock signal;
• wherein said shift register includes a predetermined second set of outputs, said memory clock generator further comprising second logic circuitry operable for receiving said second set of outputs, said second logic circuitry outputting a gating signal operable for launching a second input signal into said shift register.