Mechanism for recovery from termination of a program instruction due to an exception in a pipeland processing system

Apparatus for processing data in response to a sequence of program instructions, said apparatus comprising:

• a primary pipelined processing unit for performing data processing, said primary pipelined processing unit being responsive to a cancellation condition to cancel processing of a partially completed cancellable program instruction;
• a fix-up pipelined processing unit;
• and
• a pseudo instruction generator responsive to at least one cancellable program instruction that is subject to cancellation to generate a cancellation fix-up instruction that is issued to said fix-up pipelined processing unit, said cancellation fix-up instruction being operable upon occurrence of a cancellation condition to control said fix-up pipelined processing unit to produce a state in which said partially completed cancellable program instruction is able to be re-executed at a later time, wherein said pseudo instruction generator is operable to generate a fix-up instruction only when said cancellable program instruction comprises an instruction to overwrite the contents of a base register containing a base address for a data processing operation specified by said cancellable instruction.

Apparatus for processing data in response to a sequence of program instructions, said apparatus comprising:

• a primary pipelined processing unit for performing data processing, said primary pipelined processing unit being responsive to a cancellation condition to cancel processing of a partially completed cancellable program instruction;
• a fix-up pipelined processing unit;
• and
• a pseudo instruction generator responsive to at least one cancellable program instruction that is subject to cancellation to generate a cancellation fix-up instruction that is issued to said fix-up pipelined processing unit, said cancellation fix-up instruction being operable upon occurrence of a cancellation condition to control said fix-up pipelined processing unit to produce a state in which said partially completed cancellable program instruction is able to be re-executed at a later time, wherein said pseudo instruction generator is operable in response to a cancellable program instruction that overwrites the contents of a base register containing a base address for a data processing operation specified by said cancellable instruction to generate a cancellation fix-up instruction that reads an initial value from said base register prior to it being overwritten.

Apparatus for processing data in response to a sequence of program instructions, said apparatus comprising:

• a primary pipelined processing unit for performing data processing, said primary pipelined processing unit being responsive to a cancellation condition to cancel processing of a partially completed cancellable program instruction;
• a fix-up pipelined processing unit;
• and
• a pseudo instruction generator responsive to at least one cancellable program instruction that is subject to cancellation to generate a cancellation fix-up instruction that is issued to said fix-up pipelined processing unit, said cancellation fix-up instruction being operable upon occurrence of a cancellation condition to control said fix-up pipelined processing unit to produce a state in which said partially completed cancellable program instruction is able to be re-executed at a later time, wherein upon detection that no cancellation of said cancellable program instruction will occur, said cancellation fix-up instruction is cancelled.

Apparatus for processing data in response to a sequence of program instructions, said apparatus comprising:

• a primary pipelined processing unit for performing data processing, said primary pipelined processing unit being responsive to a cancellation condition to cancel processing of a partially completed cancellable program instruction;
• a fix-up pipelined processing unit;
• and
• a pseudo instruction generator responsive to at least one cancellable program instruction that is subject to cancellation to generate a cancellation fix-up instruction that is issued to said fix-up pipelined processing unit, said cancellation fix-up instruction being operable upon occurrence of a cancellation condition to control said fix-up pipelined processing unit to produce a state in which said partially completed cancellable program instruction is able to be re-executed at a later time, wherein if said cancellable program instruction is a block memory access instruction to memory locations specified by a base address value stored in a base address register and said cancellable program instruction does not involve writing to said base register, then said cancellation fix-up instruction is a no-operation instruction, said no-operation instruction serving to prevent subsequent instructions from being executed by said apparatus until the abort status of said block memory access instruction is resolved.

Apparatus for processing data in response to a sequence of program instructions, said apparatus comprising:

• a primary pipelined processing unit for performing data processing, said primary pipelined processing unit being responsive to a cancellation condition to cancel processing of a partially completed cancellable program instruction;
• a fix-up pipelined processing unit;
• and
• a pseudo instruction generator responsive to at least one cancellable program instruction that is subject to cancellation to generate a cancellation fix-up instruction that is issued to said fix-up pipelined processing unit, said cancellation fix-up instruction being operable upon occurrence of a cancellation condition to control said fix-up pipelined processing unit to produce a state in which said partially completed cancellable program instruction is able to be re-executed at a later time, wherein said pseudo-instruction generator is operable to issue said cancellation fix-up instruction to said fix-up pipelined processing unit in the same processing cycle that said primary pipelined processing unit receives said cancellable data processing instruction.

A method of processing data in response to a sequence of program instructions, comprising the steps of:

• issuing a cancellable program instruction that can be subject to cancellation to a primary pipelined processing unit for performing data processing, said primary pipelined processing unit being responsive to a cancellation condition to cancel processing of a partially completed cancellable program instruction;
• generating a cancellation fix-up instruction with a pseudo instruction generator in response to said cancellable program instruction, wherein said pseudo instruction generator is operable to generate a fix-up instruction only when said cancellable program instruction comprises an instruction to overwrite the contents of a base register containing a base address for a data processing operation specified by said cancellable instruction;
• and
• issuing said cancellation fix-up instruction to a fix-up pipelined processing unit, said cancellation fix-up instruction being operable upon occurrence of a cancellation condition to control said fix-up pipelined processing unit to produce a state in which said partially completed cancellable program instruction may be re-executed at a later time.

A method of processing data in response to a sequence of program instructions, comprising the steps of:

• issuing a cancellable program instruction that can be subject to cancellation to a primary pipelined processing unit for performing data processing, said primary pipelined processing unit being responsive to a cancellation condition to cancel processing of a partially completed cancellable program instruction;
• generating a cancellation fix-up instruction with a pseudo instruction generator in response to said cancellable program instruction, wherein said pseudo instruction generator is operable in response to a cancellable program instruction that overwrites the contents of a base register containing a base address for a data processing operation specified by said cancellable instruction to generate a cancellation fix-up instruction that reads an initial value from said base register prior to it being overwritten;
• and
• issuing said cancellation fix-up instruction to a fix-up pipelined processing unit, said cancellation fix-up instruction being operable upon occurrence of a cancellation condition to control said fix-up pipelined processing unit to produce a state in which said partially completed cancellable program instruction may be re-executed at a later time, wherein said cancellation fix-up instruction is operable to overwrite said base register with said initial value in response to detection of said cancellation condition.