Method and implementation of statistical detection of read after write and write after write hazards

A method for detecting instruction dependencies, comprising:

• receiving first and second pluralities of operand addresses corresponding to first and second pluralities of operands of instructions;
• selecting a register addresss;
• generating first and second logic signals in response to matches between the register address and ones of the first and second pluralities of operand addresses, respectively;
• and
• generating a signal for a dependency in response to the first and second logic signals originating from matches for the operands of different instructions.

A method for detecting instruction dependencies, comprising:

• receiving first and second pluralities of operand addresses corresponding to first and second pluralities of operands of instructions;
• selecting one of the first plurality of operands, the one of the first plurality of operands having an associated first register address and being a destination operand of a first instruction;
• selecting one of the second plurality of operands, the one of the second plurality of operands having an associated second register address;
• and
• generating a logic signal for a dependency in response to the first and second register addresses matching, and the ones of the first and second pluralities of operands being operands from different instructions.

An apparatus, comprising:

• a generating hardware structure to generate a sequence of instructions, the instructions including at least two operand addresses, wherein at least one of the at least two operand addresses is a source address;
• and
• a dependency detector coupled to the hardware structure to select a plurality of instruction groups, the instruction groups to include a plurality of randomly chosen consecutive instructions, the dependency detector to compare at least one first instruction operand address to a subset of register values equal to less than all register address values available;
• and
• the dependency detector to exclude one or more instructions' operand sources or destinations included in the plurality of groups excludes one or more operand sources and operand destinations of the instructions included in the sequence of instructions to compare to register address values available.

An apparatus, comprising:

• a generating hardware structure to generate a sequence of instructions, the instructions including at least two operand addresses, wherein at least one of the at least two operand addresses is a source address;
• a dependency detector coupled to the hardware structure to select a plurality of groups of the instructions to detect invalid combinations within each group;
• wherein the dependency detector includes:
• a first multiplexer to randomly select operand sources to compare to register addresses available;
• and a second multiplexer to randomly select operand destinations to compare to register addresses available.