Processor to execute in parallel plurality of instructions using plurality of functional units, and instruction allocation controller

An instruction allocation controller to predetermine which of a plurality of functional units is used to execute each of a plurality of instructions for a processor including said plurality of functional units, and executing said program using said plurality of functional units by processing a packet having a plurality of fields corresponding to said plurality of functional units and in which a plurality of instructions in a program are stored,

• said processor including a register storing control information as to execution control of said program, and accessed in common by said plurality of functional units,
• said instruction allocation controller comprising:
• a read unit sequentially reading in said instruction from said program, and
• a storage unit allocating and storing said instruction read in by said read unit to any field in said packet,
• said storage unit including
• a simultaneous access determination unit to determine whether a content of said register is accessed simultaneously or not when a subsequent instruction read in by said read unit and a prior instruction already stored in said packet are executed in parallel,
• an allocation determination unit responsive to determination of simultaneous access by said simultaneous access determination unit to determine whether said prior instruction and said subsequent instruction can be allocated to said plurality of fields in a same packet according to a predetermined priority, and
• an allocation unit to allocate said prior instruction and said subsequent instruction to respective plurality of fields in said same packet so that said prior instruction and said subsequent instruction are executed in parallel in response to determination of admissible allocation by said allocation determination unit, and to allocate said prior instruction and said subsequent instruction to respective plurality of fields in said same packet so that said prior instruction and said subsequent instruction are executed serially in response to determination of inadmissible allocation by said allocation determination unit,
• wherein said predetermined priority is the priority among said plurality of functional units as to access of said control information.