Dynamic variable page size translation of addresses
AssigneeFujitsu Limited
InventorVydhyanathan Kalyanasundharam
Life of this patent
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Abstract
The current disclosure concerns dynamic variable page size translation of addresses. Such translation can be achieved at higher clock speeds than have heretofore been possible due to the use of a translation lookaside buffer (TLB) with RAM cells which eliminate the need to utilize circuitry external to the TLB. Such translation can also be bypassed at higher speeds than have heretofore been possible due to the use of translation bypass circuitry which eliminates the need to utilize circuitry external to the TLB.
Claims20
A translation look-aside buffer for translating received virtual addresses into physical addresses in a variable page size memory having N page sizes wherein N is an integer greater than 1, the translation look-aside buffer comprising:
- a content addressable memory for storing virtual address tags and for matching the received virtual addresses to the address tags to thereby generate CAM match signals each referencing a page table entry;
- and
- plural page table entries coupled to the content addressable memory for targeted action based on the CAM match signal, each page table entry storing physical address data corresponding to respective virtual address data and comprising:
- a plurality of first-type memory cells grouped into N−1 cell groups, each first-type memory cell storing a single physical address bit;
- and
- N−1 second-type memory cells, each second-type memory cell coupled to a cell group and storing size-field data associated with the coupled cell group, the physical address data stored in the coupled cell group being output responsive to the size-field data is in a first state, and received virtual address bits corresponding to the coupled cell group being output responsive to the size-field data is in a second state.
A translation look-aside buffer for translating virtual addresses comprised of virtual address bits into physical addresses, the translation look-aside buffer comprising:
- a content addressable memory for storing virtual address tags corresponding to the virtual addresses;
- and
- a page table entry array coupled to the content addressable memory and receiving the virtual addresses, the page table entry array including a plurality of page table entries for storing physical addresses corresponding to respective ones of the virtual addresses tags, each page table entry comprising:
- a physical address cell group, each physical address cell in the cell group storing a single physical address bit;
- and
- a size-field memory cell coupled to the cell group and storing size-field data associated with the cell group,
- the page table entry array outputting the physical address bits stored in the cell group responsive to the size-field data is in a first state, and the page table entry array outputting the virtual address bits responsive to the size-field data is in a second state.
A method of using a translation look-aside buffer to translate received virtual address data into physical address data, the translation look-aside buffer comprising at least one page table entry having at least one two-state size-field cell with size-field data stored therein and at least one physical address cell group with physical address data stored therein and directly coupled to the size-field cell, the method comprising:
- receiving, at the page table entry, virtual address data corresponding to the physical address data stored in the cell group;
- reading the size-field data stored in the size-field cell;
- selecting, as an output from the page table entry and as part of the translated physical address data, the physical address data stored in the cell group responsive to the size-field cell is in a first state;
- and
- selecting, as an output from the page table entry and as part of the translated physical address data, the received virtual address data responsive to the size-field is in a second state.
A translation look-aside buffer of a variable page size memory having a plurality of page sizes for translating received virtual address data into translated physical address data, the translation look-aside buffer comprising:
- a content addressable memory comprising a plurality of memory cells for storing virtual address tags corresponding to the received virtual address data, the content addressable memory generating a match signal referencing a page table entry which corresponds to one of the stored virtual address tags;
- and
- a page table entry array coupled to the content addressable memory and including a plurality of page table entries which each store physical address data, the array being capable of receiving a generated match signal and identifying a unique page table entry referenced by the match signal, each page table entry comprising:
- a plurality of first-type memory cell groups, each cell group comprising a plurality of first-type memory cells and each first-type memory cell storing one physical address bit;
- and
- a plurality of second-type memory cells, each second-type memory cell coupled to a first-type cell group and storing size-field data associated with the coupled cell group, the physical address data stored in the coupled cell group being output responsive to the size-field data is in a first state, and the received virtual address data corresponding to the coupled cell group being output responsive to the size-field data is in a second state.
A memory cell for a translation look-aside buffer which receives virtual address data corresponding to physical address data, stores size field data indicative of the page size of a memory and generates a read signal, the memory cell comprising:
- a physical address latch for storing a single physical address bit of the physical address;
- a multiplexer coupled to the physical address latch, the multiplexer comprising at least a first and second multiplexer inputs, a select-signal input and a multiplexer output, the first input receiving the address bit from the physical address latch, the second input receiving a virtual address bit of the received virtual address data, and the select-signal input receiving the size-field data, the multiplexer outputting the physical address bit responsive to the size-field data is in a first state and outputting the virtual address bit responsive to the size-field data is in a second state;
- and
- dynamic read circuitry coupled to the multiplexer for outputting from the memory cell the multiplexer output in response to the read signal.
A dynamic variable page size translation look-aside buffer for translating virtual addresses into physical addresses in a variable page size memory having a plurality of page sizes, the translation look-aside buffer comprising:
- means for storing virtual address tags which correlate the virtual addresses to the physical addresses;
- and
- means for storing page table entries coupled to the means for storing virtual address tags, each page table entry corresponding to one of the virtual address tags and storing a physical address, each page table entry comprising:
- a plurality of physical address memory cell groups, each cell group including at least one cell and storing physical address data;
- a plurality size-field memory cells coupled to respective ones of the physical address cell groups and storing size-field data for respective ones of the cell groups;
- means for outputting the physical address data of a particular cell group when the data stored in the size-field cell which is coupled to the particular cell group is in a first state;
- means for outputting virtual address data corresponding to the physical address data of a particular cell group when data stored in the size-field cell which is coupled to the particular cell group is in a second state.
A method of managing data in a translation look-aside buffer of a variable page size memory using virtual addresses corresponding to physical addresses, the virtual memory having N page sizes wherein N is an integer greater than 1 and each of the virtual addresses comprising a plurality of virtual address bits, the method comprising:
- storing physical address data, the physical address data grouped into N−1 groups and each group comprising a plurality of physical address bits;
- storing N−1 size-field data coupled to the respective N−1 groups, each of the size-field data being stored in a first state when the physical address bits in the coupled group will be used to generate the physical address and the size-field data being stored in a second state when the virtual address bits corresponding to the coupled group will be used to generate the physical address;
- responsive to a data request which includes the virtual address, outputting a translated physical address that corresponds to the virtual address, comprising:
- outputting the physical address bits stored in the coupled cell group responsive to the size-field is in the first state;
- and
- outputting the virtual address bits corresponding to the coupled cell group responsive to the size-field is in the second state.
A method of managing data in a translation look-aside buffer of a variable page size virtual memory using virtual addresses corresponding to physical addresses, the virtual memory having N page sizes wherein N is an integer greater than 1 and each of the virtual addresses comprising a plurality of virtual address bits, the method comprising:
- storing physical address data, the physical address data grouped into N−1 groups and each group comprising a plurality of physical address bits;
- and
- storing N−1 size-field data coupled to the respective N−1 groups, each of the size-field data being stored in a first state when the physical address bits in the coupled group will be used to generate the physical address and the size-field data being stored in a second state when the virtual address bits corresponding to the coupled group will be used to generate the physical address.
A method of using a translation look-aside buffer to translate received virtual addresses into translated physical addresses during a single two-phase timing cycle, the translation look-aside buffer comprising a content addressable memory and a page table entry array with a plurality of page table entries coupled to the content addressable memory, each page table entry comprising at least one physical address cell group for storing physical address data potentially corresponding to a received virtual address, each page table entry further comprising at least one two-state size-field cell coupled to the cell group, the method comprising:
- during the first phase of the timing cycle:
- receiving a virtual address at both the content addressable memory and the page table entry array;
- using the content addressable memory to convert the received virtual address into a match signal which references one of the page table entries in the array;
- and
- using the virtual address to precharge the physical address cell group of at least one page table entry;
- and
- during the second phase of the timing cycle:
- receiving the match signal at the page table entry array;
- outputting, as a portion of the translated physical address, the physical address data from the cell group of the page table entry referenced by the match signal responsive to the coupled size-field cell is in a first state;
- and
- outputting, as a portion of the translated physical address, the received virtual address data corresponding to the physical address data stored in the cell group of the page table entry referenced by the match signal responsive to the size-field cell is in a second state.
Dependencies are inferred from the claim text.