Semiconductor memory device capable of performing a write operation 1 or 2 cycles after receiving a write command without a dead cycle

A data processing method for a semiconductor memory device comprising:

• address input control means for outputting a read address from the outside, delaying an output of a write address by 1 cycle during the execution of a write operation after 1 cycle, and delaying an output of the write address by 2 cycles during the execution of the write command after 2 cycles;
• data input control means for delaying by 0 cycle or 1 cycle an output of write data inputted from the outside after 1 cycle during the execution of the write operation after the 1 cycle, and delaying by 0 cycle, 1 cycle and 2 cycles the output of the write data inputted from the outside after 2 cycles during the execution of the write operation after 2 cycles;
• wherein the data input control means reads the data from a cell pertinent to a read address from the address input control means, outputs the data through the flow through method during the execution of the write operation after the 1 cycle, outputs the data through the pipelined method during the execution of the write operation after the 2 cycles, and writes the data transmitted to the data transmission control means to a cell pertinent to a write address from the address input control means;
• wherein the data delayed by 0 cycle is transmitted to the predetermined number of cells when write, write command is continuously inputted during the execution of the write operation after the 1 cycle, wherein the data delayed by 1 cycle is transmitted to the predetermined number of cells when read, write command is continuously inputted, wherein the data delayed by 0 cycle is transmitted to the predetermined number of cells when write, write, write command is continuously inputted during the execution of the write command after the 2 cycles, wherein the data delayed 1 cycle is transmitted to the predetermined number of cells when write, read, write command is continuously inputted or when read, write, write command is continuously inputted, and wherein the data delayed by 2 cycle is transmitted to the predetermined number of cells when read, read, write command is continuously inputted.

A method for processing data in a semiconductor memory device, comprising:

• receiving an external write or read address;
• if the read address is received, reading data from a cell corresponding to the read address;
• if the write address is received, delaying the write address by 1 cycle when the memory device operates in a write after 1 cycle mode or by 2 cycles when the memory device operates in a write after 2 cycles mode;
• receiving external write data;
• delaying the write data by a first or second predetermined number of cycles when the memory device operates in the write after 1 cycle mode or by a third or fourth predetermined number of cycles when the memory device operates in the write after 2 cycles mode;
• transmitting the write data delayed by the first predetermined number of cycles responsive to a first command sequence;
• transmitting the write data delayed by the second predetermined number of cycles responsive to a second command sequence;
• transmitting the write data delayed by the third predetermined number of cycles responsive to a third command sequence;
• transmitting the write data delayed by the fourth predetermined number of cycles responsive to a fourth command sequence;
• and
• writing the write data to a cell corresponding to the write address;
• wherein the first predetermined number of cycles is 0, the second predetermined number of cycles is 1, the third predetermined number of cycles is 0, and the fourth predetermined number of cycles is either 1, or 2;
• and
• wherein the first command sequence is a write, write command sequence, the second command sequence is a read, write command sequence, the third command sequence is a write, write, write command sequence, and the fourth command sequence is a write, read, write or write, read, read command sequence.