Pipelined SDRAM memory controller to optimize bus utilization

A pipelined SDRAM memory controller to optimize DRAM bus utilization, comprising:

• a priority arbitration unit for receiving requests from devices and determining the priority for said requests to send a granted request with highest priority;
• a page controller for receiving said granted request and monitoring DRAM module internal state;
• a command generator for generating background commands and foreground commands based on said granted request received by said page controller and generating required information;
• a background queue for storing said background commands and said required information;
• a foreground queue for storing said foreground commands and said required information;
• a background finite state machine controller for issuing a pointed background command from said background queue onto DRAM interface when background conditions are satisfied;
• and
• a foreground finite state machine controller for issuing a pointed foreground command from said foreground queue onto DRAM interface when foreground conditions are satisfied;
• wherein said required information includes a row address, a column address, bank information, access length, a cycle ID, an ordering ID, and an ordering flag, and wherein said background conditions are that,
• said background queue is not empty;
• said command bus is not occupied by a foreground command;
• all DRAM AC timing for said background command are met;
• the pointed background command does not terminate the useful ongoing data transfer;
• and
• if the pointed background command accompanied with valid ordering flag, the pointed background command meets an ordering management, and
• wherein said ordering criterion is that the pointed background command with valid ordering flag is issued only when the cycle ID of the pointed foreground command is larger than the ordering ID of the pointed background command.

A pipelined SDRAM memory control method to optimize DRAM bus utilization, comprising the steps of:

• selecting a request with highest priority as a granted request by a priority arbitration unit when memory requests are asserted;
• decoding address of said granted request into a row address and a column address;
• generating an incremental cycle ID;
• generating proper commands for said granted request and classifying the commands into background commands and foreground commands;
• assigning said incremental cycle ID to every said granted request;
• pushing the background commands and the foreground commands accompanied with required information into a background queue and a foreground queue, respectively;
• and
• issuing a pointed background command when background conditions are satisfied or a pointed foreground command when foreground conditions are satisfied onto command bus in a pipelined way;
• wherein said required information includes said row address, said column address, said cycle ID, an ordering ID, an ordering flag, bank information, and access length, and wherein said ordering ID is generated for said background commands which are classified from the commands and the pointed background command is issued when said ordering ID is equal to the largest cycle ID of said foreground commands stored in said foreground queue, and
• wherein said background conditions are that:
• said background queue is not empty;
• said command bus is not occupied by a foreground command;
• all DRAM AC timing for said background command are met;
• the pointed background command does not terminate the useful ongoing data transfer;
• and
• if the pointed background command accompanied with valid ordering flag, the pointed background command meets an ordering criterion, and wherein said ordering criterion is that the pointed background command with valid ordering ID is issued only when the cycle ID of the pointed foreground command is larger than the ordering ID of said pointed background command.