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AssigneeInternational Business Machines Corporation
InventorsRavi Kumar Arimilli, Lakshminarayana Baba Arimilli, John Steven Dodson, Guy Lynn Guthrie, William John Starke
Estimating the term…
A multiprocessor data processing system requires careful management to maintain cache coherency. Conventional systems using a MESI approach sacrifice some performance with inefficient lock-acquisition and lock-retention techniques. The disclosed system provides additional cache states, indicator bits, and lock-acquisition routines to improve cache performance. In particular, as multiple processors compete for the same cache line, a significant amount of processor time is lost determining if another processor's cache line lock has been released and attempting to reserve that cache line while it is still owned by the other processor. The preferred embodiment provides an additional cache state which specifically indicates that a processor has released its lock on a cache line after it has performed any necessary modifications.
A method, in a data processing system including a plurality of processors and a multiple-level memory hierarchy maintaining coherency using a coherency protocol, said method comprising:
A system for supporting memory updates in a data processing system including a plurality of processors and a multiple-level memory hierarchy maintaining coherency using a coherency protocol, comprising:
A system, comprsing:
Dependencies are inferred from the claim text.