Cache structure for storing variable length data
AssigneeIntel Corporation
InventorsLihu Rappoport, Stephan J. Jourdan, Ronny Ronen
Life of this patent
Estimating the term…
Abstract
A cache architecture is adapted to store data items of variable length. Given appropriate circumstances, the cache architecture permits multiple data items to be retrieved from the cache in single clock cycle. The cache architecture may find application in a front end processing system of a processor storing instruction segments. If a first instruction segment does not occupy the full width of the cache, other instruction segments can be retrieved from the cache simultaneously with the first instruction segment. The cache may be organized into a plurality of cache banks, each cache bank being independently addressed. Each bank may consist of several cache ways.
Claims18
A method of retrieving variable length data items stored in a cache having a predetermined number N of banks, comprising:
- for a first data item to be read, determining a first number from 1 to N of the banks said first number indicating a number of the banks in which the first data item is stored,
- identifying and addressing the banks that store the first data item,
- for a second data item to be read, determining a second number from 1 to N of the banks said second number indicating a number of the banks in which the second data item is stored,
- addressing cache entries of any bank storing the second data item that does not overlap with the banks storing the first data item, and
- simultaneously reading data from all the addressed cache entries.
A method of retrieving variable length instruction segments stored in multiple banks of a cache, comprising:
- for a first instruction segment to be read, identifying the banks in which portions of the first instruction segment is stored,
- addressing cache entries within the identified banks that store the first instruction segment,
- for a second instruction segment to be read, identifying banks in which portions of the second instruction segment is stored,
- addressing cache entries of any bank storing the second instruction segment that does not overlap with the banks storing the first instruction segment, and
- simultaneously reading data from all the addressed cache entries.
A cache system, comprising:
- a plurality of cache banks, each having entries of a predetermined width, the cache banks to store instruction segments, an instruction segment being stored in from one to all of the banks, and
- an address generator:
- responsive to an instruction pointer of a desired first instruction segment, to identify which of the banks store portions of the first instruction segment and to address the identified banks, wherein from one to all of the banks are identified, and
- responsive to an instruction pointer of a desired second instruction segment, to identify which of the banks store portions of the second instruction segment, to determine if any of the banks storing portions of the second instruction segment are non-overlapping with the banks storing portions of the first instruction pointer and, if so, to address the non-overlapping banks.
Dependencies are inferred from the claim text.