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US 6,549,984 B1Granted
Multi-bus access cache
AssigneeIntel Corporation
InventorsDan W. Patterson, Stephen H. Hunt
Life of this patent
Estimating the term…
Abstract
An apparatus and method are disclosed for providing concurrent access to first storage area and a second storage area. According to one embodiment, a device includes the first storage area. The device and the second storage area are both coupled to a first bus and are coupled together by a dedicated second bus. According to one embodiment, a snoop operation on the first storage area be preferred concurrently with a snoop operation on the second storage area.
Claims20
A computer system comprising:
- a processor, the processor including a first cache memory, the first cache memory being a first level cache for the processor;
- a second cache memory outside the processor, the second cache memory being a second level cache for the processor;
- a dedicated backside bus, the dedicated backside bus coupling the processor to the second cache memory, the dedicated backside bus being dedicated to the transfer of data between the processor and the second cache memory;
- and
- a system bus, the second cache memory being operable to perform a snoop operation on the system bus concurrently at least in part with a transaction between the processor and the second cache memory using the dedicated backside bus, the transaction comprising the transfer of modified data from the second cache memory to the processor.
2 more elements
A method comprising:
- detecting activity on a system bus on which a processor and a second memory cache to the processor reside, the processor including a first memory cache, the first memory cache being a first level cache for the processor and the second memory cache being a second level cache for the processor, the processor and the second memory cache being coupled together by a dedicated backside bus;
- in response to the activity on the system bus, the first memory cache performing a snoop operation on the first bus concurrently at least in part with a transaction between the processor and the second memory cache using the dedicated backside bus, the transaction comprising the transfer of modified data from the second cache memory to the processor.
A cache memory comprising:
- a data array to store cached data from a higher level storage device;
- a tag array associated with the data array to store a unique tag for each item of data stored in the data array to allow a determination to be made regarding whether data associated with a particular memory address is currently stored in the data array;
- a backside bus interface coupled with a backside bus of a computer system to provide a dedicated communication interface between a processor of the computer system and the cache memory;
- a system bus interface coupled with a system bus of the computer system to which the processor is also coupled;
- and
- a bus logic circuit coupled to the system bus interface and the backside bus interface to arbitrate access to the tag array and the data array by the system bus interface and the backside bus interface and capable of performing a snoop operation on the system bus in response to a transaction on the system bus in parallel at least in part with a transaction on the backside bus, the transaction on the backside bus comprising the transfer of modified data from the cache memory to the processor.
3 more elements
A computer system comprising:
- a processor, the processor including a first cache memory, the first cache memory being a first level cache for the processor;
- a second cache memory outside the processor, the second cache memory being a second level cache for the processor;
- a dedicated backside bus, the dedicated backside bus coupling the processor to the second cache memory, the dedicated backside bus being dedicated to the transfer of data between the processor and the second cache memory;
- and
- a system bus, the second cache memory being operable to perform a snoop operation on the system bus concurrently with a transaction between the processor and the second cache memory using the dedicated backside bus, the transaction comprising the transfer of modified data from the second cache memory to the processor.
2 more elements
A method comprising:
- detecting activity on a system bus on which a processor and a second memory cache to the processor reside, the processor including a first memory cache, the first memory cache being a first level cache for the processor and the second memory cache being a second level cache for the processor, the processor and the second memory cache being coupled together by a dedicated backside bus;
- in response to the activity on the system bus, the first memory cache performing a snoop operation on the first bus concurrently with a transaction between the processor and the second memory cache using the dedicated backside bus, the transaction comprising the transfer of modified data from the second cache memory to the processor.
A cache memory comprising:
- a data array to store cached data from a higher level storage device;
- a tag array associated with the data array to store a unique tag for each item of data stored in the data array to allow a determination to be made regarding whether data associated with a particular memory address is currently stored in the data array;
- a backside bus interface coupled with a backside bus of a computer system to provide a dedicated communication interface between a processor of the computer system and the cache memory;
- a system bus interface coupled with a system bus of the computer system to which the processor is also coupled;
- and
- a bus logic circuit coupled to the system bus interface and the backside bus interface to arbitrate access to the tag array and the data array by the system bus interface and the backside bus interface and capable of performing a snoop operation on the system bus in response to a transaction on the system bus in parallel with a transaction on the backside bus, the transaction on the backside bus comprising the transfer of modified data from the cache memory to the processor.
3 more elements
Dependencies are inferred from the claim text.