Tri-stating output buffer during initialization of synchronous memory

A synchronous flash memory device comprising:

• a memory array of non-volatile memory cells;
• an output buffer to output data from the memory array;
• a tri-state logic circuit to selectively tri-state the output buffer during initialization;
• and
• control circuitry to signal the tri-state logic circuit to tri-state the output buffer during memory initialization.

A synchronous memory device comprising:

• a memory array;
• an output buffer to output data from the memory array;
• and
• a tri-state logic circuit to selectively tri-state the output buffer for a predefined period of time upon commencement of memory initialization.

A memory system comprising:

• an external processor;
• and
• a synchronous memory coupled to the external processor, the synchronous memory comprising,
• a memory array,
• an output buffer to output data from the memory array,
• a tri-state logic circuit to selectively tri-state the output buffer, and
• control circuitry to signal the tri-state logic circuit to tri-state the output buffer during memory initialization.

A method of operating a memory, comprising:

• starting initialization of the memory;
• tri-stating an output buffer of the memory;
• finishing initialization of the memory;
• and
• returning the output buffer to normal operation after initialization of memory is completed.

A method of operating a memory system comprising

• generating a signal to indicate the start of initialization of a memory;
• tri-stating an output buffer in response to the signal indicating the start of initialization of memory;
• generating a signal to indicate the completion of initialization of the memory;
• and
• returning the output buffer to normal operations in response to the signal indicating completion of initialization of memory.

A method of operating a memory system comprising

• starting initialization of a memory;
• tri-stating an output buffer during initialization of the memory;
• polling the memory to verify the status of initialization;
• and
• allowing an external processor to access the memory upon verification of completion of memory initialization.

A flash memory device comprising:

• a memory array of non-volatile memory cells;
• a plurality of non-volatile storage registers to contain information used during memory operations;
• a plurality of volatile storage registers, each volatile storage register being coupled to an associated one of the plurality of non-volatile storage registers;
• an output buffer to output data from the memory array;
• a plurality of data connections to provide output data;
• a tri-state logic circuit to selectively tri-state the output buffer;
• and
• control circuitry to perform initialization of the memory, wherein the control circuitry signals the tri-state logic circuit to tri-state the output buffer during initialization of the memory.

A method of operating a memory system comprising:

• starting initialization of the memory;
• tri-stating an output buffer of the memory;
• transferring information from non-volatile storage registers to volatile storage registers;
• finishing initialization of the memory;
• and
• returning the output buffer to normal operation after initialization of memory is completed.

A synchronous memory device comprising:

• a memory array;
• an output buffer to output data from the memory array;
• a tri-state logic circuit to selectively tri-state the output buffer;
• and
• control circuitry to generate a control signal to cause the tri-state logic circuit to tri-state the output buffer only during memory initialization.

A synchronous memory device comprising:

• a memory array;
• an output buffer to output data from the memory array;
• a tri-state logic circuit to selectively tri-state the output buffer;
• and
• control circuitry to signal the tri-state logic circuit to selectively tri-state the output buffer during memory initialization, the control circuitry capable of overriding the tri-state condition to provide a response to a status command request.

A synchronous flash memory device comprising:

• a memory array of non-volatile memory cells;
• an output buffer to output data from the memory array;
• a tri-state logic circuit to selectively tri-state the output buffer during initialization;
• and
• control circuitry to signal the tri-state logic circuit to tri-state the output buffer during memory initialization, the control circuitry capable of overriding the tri-state condition to provide a response to a status command request.

A memory system comprising:

• an external processor;
• and
• a synchronous memory coupled to the external processor, the synchronous memory capable of receiving a read status command from the external processor to determine the status of a memory initialization, the synchronous memory comprising,
• a memory array,
• an output buffer to output data from the memory array,
• a tri-state logic circuit to selectively tri-state the output buffer, and
• control circuitry to signal the tri-state logic circuit to tri-state the output buffer during the memory initialization.

A method for operating a memory system comprising starting initialization of a memory;

• tri-stating an output buffer during initialization of the memory;
• polling the memory to verify the status of initialization;
• allowing an external processor to access the memory upon verification of completion of memory initialization;
• and
• overriding the tri-state condition of the output buffer to signal the external processor that initialization is occurring.

A method for operating a memory comprising:

• receiving a signal to indicate the start of initialization of a memory;
• tri-stating an output buffer in response to the signal indicating the start of initialization of memory;
• receiving a signal to indicate the completion of initialization of the memory;
• and
• returning the output buffer to normal operations in response to the signal indicating completion of initialization of memory.