US 6,549,971 B1 · Cascaded differential receiver circuit

Abstract

A differential receiver circuit including first, second, and third amplification stages. The first amplification stage is configured to receive a differential input signal and to produce a single ended first output signal responsive to the differential input signal. The second amplification stage is connected in parallel with the first stage and configured to receive the differential input signal and to produce a second output signal responsive to the differential input signal. The third amplification stage is configured to receive the first and second output signals and to produce a single ended third output signal indicative of the differential in the first and second output signals. In one embodiment the differential receiver circuit further includes an inhibit circuit configured receive an inhibit control signal and to drive the p-channel devices gated to the first amplifier node and the n-channel devices gated to the second amplifier node to cutoff when the inhibit control signal is in a specified inhibit state. The inhibit circuit is preferably further configured to provide a low impedance path between the first amplifier node, the second amplifier node, and the feedback node when the inhibit control signal is in a specified functional state.

Claims21

Dependent claims

A differential receiver circuit, comprising:

a first amplification stage configured to receive a differential input signal and to produce a single ended first output signal responsive to the differential input signal;
a second amplification stage in parallel with the first stage and configured to receive the inverse of the differential input signal and to produce a second output signal responsive to the differential input signal;
and
a third amplification stage configured to receive the first and second output signals and to produce a single ended third output signal based on the difference between the first and second output signals.

1 more element

A data processing system, comprising:

at least one processor coupled to a host bus,
a system memory accessible to the at least one processor via the system bus;
a host bridge coupled between the host bus and an I/O bus;
an I/O device connected to the I/O bus via a transmission medium, wherein the I/O device includes a differential receiver circuit suitable for receiving a differential input signal comprising:
a first amplification stage configured to receive the differential input signal and to produce a single ended first output signal responsive to the differential input signal;
a second amplification stage in parallel with the first stage and configured to receive the inverse of the differential input signal and to produce a second output signal responsive to the differential input signal;
and
a third amplification stage configured to receive the first and second output signals and to produce a single ended third output signal based on the difference between the first and second output signals.

5 more elements

An I/O device including a bus interface unit for communicating with an I/O bus of a data processing system, wherein the I/O device includes a differential receiver circuit suitable for receiving a differential input signal comprising:

a first amplification stage configured to receive the differential input signal and to produce a single ended first output signal responsive to the differential input signal;
a second amplification stage in parallel with the first stage and configured to receive the inverse of the differential input signal and to produce a second output signal responsive to the differential input signal;
and
a third amplification stage configured to receive the first and second output signals and to produce a single ended third output signal based on the difference between the first and second output signals.

1 more element

Dependencies are inferred from the claim text.

Cascaded differential receiver circuit

Life of this patent

Cascaded differential receiver circuit

Life of this patent

Abstract

Claims21