Microcomputer with interrupt packets
AssigneeSTMicroelectronics S.r.l.
InventorsAndrew Michael Jones, Michael David May
Life of this patent
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Abstract
A computer system provides on chip at least one CPU connected to another module by an address and data path, the module generating interrupt request packets with a destination address, the CPU decoding the packet, identifying a priority for the interrupt request and selectively responding to the request.
Claims14
A computer system comprising an integrated circuit device with an address and data path for distributing addressed bit packets and interconnecting a plurality of on-chip devices including at least one CPU and at least one other module, the module having circuitry responsive to an event to generate an interrupt request packet with a destination address and to place the interrupt request packet onto the address and data path, said CPU having event logic to decode the packet, identify a priority for the interrupt request and selectively respond to the request of the packet depending on the priority of the interrupt request.
A method of operating a computer system comprising an integrated circuit device with an address and data path interconnecting a plurality of on-chip devices including at least one CPU and at least one other module, which method comprises detecting an event at a module, generating an interrupt request packet with a destination address, distributing the request packet on the address and data path to the destination CPU, decoding the packet at the destination to identify a priority for the interrupt request and selectively responding to the request of the packet depending on the priority of the interrupt request.
Dependencies are inferred from the claim text.