US 6,549,926 B1 · SRT divider having several bits of each partial remainder one-hot encoded to minimize the logic levels needed to estimate quotient bits

Abstract

A Sweeney, Robertson, Tocher (SRT) divider for use in a computer system has recoding circuitry to recode the three most significant bits of the dividend into one-hot form as the dividend is loaded into a quotient/partial remainder register. With each clock, a partial remainder is generated also having its most significant three bits in one-hot form and the remaining bits in binary encoded form. The divider has several stages permitting it to generate several bits of quotient in each clock cycle. Each stage has circuitry for estimating a quotient digit, and for computing a partial remainder by subtracting the product of the quotient digit times the divisor from either the dividend or a previous partial remainder. This subtraction is performed upon a one-hot code in the most significant bits and in binary code on the least significant bits. The divider also has circuitry for assembling a plurality of quotient digits into a quotient.

Claims10

Dependent claims

A divider for use in a computer system, the divider dividing a dividend V by a divisor D and producing a quotient Q, the divider comprising:

circuitry for estimating a quotient digit Qn;
circuitry for computing a partial remainder Rn by subtracting P, the product of the quotient digit Qn times the divisor D, from a value selected from the set consisting of the dividend and a previous partial remainder Rn−1, the effectively most significant bits of partial remainder Rn being one-hot encoded with less significant bits of Rn being binary coded, and the effectively most significant bits of the set consisting of the dividend V and the previous partial remainder Rn−1 being one-hot encoded;
and
circuitry for assembly the quotient digit Qn into a quotient.

1 more element

A computer program product for performing division in a computer system, the division dividing a dividend V by a divisor D to produce a quotient Q, the computer program product comprising instructions for:

a) recoding at least two most significant bits of the dividend V into one-hot encoded form;
b) estimating a quotient digit Q1;
c) computing P1, a product of the quotient digit Q1 times the divisor D;
d) computing a partial remainder R1, by subtracting P1 from the dividend V;
e) estimating an additional quotient digit Qn, where n is initially 1;
f) computing Pn, the product of the quotient digit Qn times the divisor D;
g) computing a partial remainder Rn, by subtracting Pn from the previous partial remainder Rn−1, where Rn−1 is initially R1, and wherein at least two of the most significant bits of partial remainder Rn are in one-hot encoded form.
h) repeating steps (e), (f), and (g) as required to produce all necessary bits of the quotient;
and
i) assembling the quotient digits Q1 and at least one quotient digit Qn into a quotient.

7 more elements

Dependencies are inferred from the claim text.

SRT divider having several bits of each partial remainder one-hot encoded to minimize the logic levels needed to estimate quotient bits

Life of this patent

SRT divider having several bits of each partial remainder one-hot encoded to minimize the logic levels needed to estimate quotient bits

Life of this patent

Abstract

Claims10