US 6,549,598 B1Granted

Clock signal extraction circuit

AssigneeAdvantest Corporation

InventorNorio Kumaki

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Abstract

A clock signal extraction circuit extracts clock information from the received data and reproducing the clock signal. The clock signal extraction circuit includes an input terminal for receiving serial data having time periods each being an integer multiple of a fundamental time period of a clock signal to be reproduced, a delay element for providing a predetermined delay time to the serial data, a voltage controlled oscillator (VCO) whose oscillaticon frequency is regulated by a control signal voltage for producing the clock signal, a latch circuit for latching the serial data at the timing cf the clock signal from the VCO, a phase comparator for comparing the serial data from the delay element and the latched serial data from the latch circuit and generating a detection signal representing a phase difference therebetween, and a PLL for feed-backing the detection signal to the VCO as the control signal voltage.

Claims18

Dependent claims

A clock signal extraction circuit, comprising:

an input terminal for receiving serial data having time periods each being an integer multiple of a fundamental time period of a clock signal to be reproduced;
a delay element for providing a predetermined delay time to the serial data from the input terminal;
a voltage controlled oscillator whose oscillation frequency is regulated by a control signal voltage for producing the clock signal;
means for latching the serial data at the timing of the output signal of the voltage controlled oscillator;
a phase comparator for comparing the serial data from the delay element and the latched serial data from the latching means and generating a detection signal representing a phase difference therebetween;
and
means for feed-backing the detection signal to the voltage controlled oscillator as the control signal voltage to minimize the phase difference detected by the phase comparator;
wherein said predetermined delay time by said delay element is adjusted so that timings of the serial data from the delay element and the latched serial data from the latching means are equivalent to one another;
and
wherein said phase comparator detects the phase difference by comparing edges of the time periods in the serial data, thereby increasing a phase detection gain.

7 more elements

A clock signal extraction circuit, comprising:

an input terminal for receiving serial data having time periods each being an integer multiple of a fundamental time period of a clock signal to be reproduced;
a delay element for providing a predetermined delay time to the serial data from the input terminal;
a voltage controlled oscillator whose oscillation frequency is regulated by a control signal voltage for producing the clock signal;
a flip-flop circuit provided with the serial data from the input terminal and the output signal of the voltage controlled oscillator for latching the serial data at the timing of the output signal of the voltage controlled oscillator;
a phase comparator for comparing the serial data from the delay element and the latched serial data from the flip-flop circuit and generating a detection signal representing a phase difference therebetween;
and
means for feed-backing the detection signal to the voltage controlled oscillator as the control signal voltage to minimize the phase difference between detected by the phase comparator;
wherein said predetermined delay time by said delay element is adjusted to be greater than a sum of a set-up time and a signal propagation delay time of the flip-flop circuit and a length of jitter superimposed on the serial data;
and
wherein said phase comparator detects the phase difference by comparing edges of the time periods in the serial data, thereby increasing a phase detection gain.

7 more elements

A clock signal extraction circuit, comprising:

an input terminal for receiving serial data having time periods each being an integer multiple of a fundamental time period of a clock signal to be reproduced;
a delay element for providing a predetermined delay time to the serial data from the input terminal;
a voltage controlled oscillator whose oscillation frequency is regulated by a control signal voltage for producing the clock signal;
a frequency divider for dividing the oscillation frequency of the voltage controlled oscillator by a predetermined division ratio;
a flip-flop circuit provided with the serial data from the input terminal and the output signal of the voltage controlled oscillator for latching the serial data at the timing of the output signal of the voltage controlled oscillator;
a phase comparator for comparing the serial data from the delay element and the latched serial data from the flip-flop circuit and generating a detection signal representing a phase difference therebetween;
and
means for feed-backing the detection signal to the voltage controlled oscillator as the control signal voltage to minimize the phase difference detected by the phase comparator;
wherein said predetermined delay time by said delay element is adjusted to be greater than a sum of a set-up time and a signal propagation delay time of the flip-flop circuit and a length of jitter superimposed on the serial data;
and
wherein said phase comparator detects the phase difference by comparing edges of the time periods in the serial data, thereby increasing a phase detection gain.

8 more elements

Dependencies are inferred from the claim text.