High speed phase alignment process and device
AssigneeTexas Instruments Incorporated
InventorJerome Ribo
Life of this patent
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Abstract
A device for phase alignment between a data signal and a main clock signal, characterized by the fact that, from a main clock signal, it has some means of generation of clock signals which are phase-shifted with respect to one another by a fraction of a period of said main clock signal, some means 10 of dividing the input data signal by sampling of said signal by said clock signals in order to obtain data signals with a length equal to said fraction of a period of said main clock signal, observation window 14 of said sampled data bits, said window 14 having a length equal to a data bit of the entering signal, a set of pipelines 16 for parallel processing using an algorithm of the signals transmitted by the observation window in view of retrieving data signals, and device 18, 19 for drift compensation.
Claims8
A process for alignment of phase between a data signal and a main clock signal, wherein the data signal comprises a sequence of data bits each having a data bit length, comprising the steps of:
- digitizing the data signal to form sample elements with a length equal to a fraction of a period of the main clock signal by sampling of said data signal using phase signals derived from said main clock signal which are phase-shifted with respect to one another by said fraction of a period of the main clock signal,
- observing a set of sequential sample elements of the data signal thus obtained through an observation window, wherein the observation window has a length approximately equal to the data bit length,
- moving the observation window so that a transition edge between two adjacent data bits is centered in the window,
- transmitting sets of sequential sample elements thus observed to a plurality of pipelines such that each of the plurality of pipelines receives a different set of sequential sample elements, and
- processing each set of sequential sample elements in each of the plurality of pipelines in a parallel manner to recover a data bit contained therein.
A phase alignment device for alignment of phase between a data signal and a main clock signal, comprising:
- means of generation, from a main clock signal, of clock signals which are phase-shifted with respect to one another by a fraction of a period of said main clock signal,
- drift compensation unit 18, 19 which uses as input the data coming from a pipelines 16 and provides data in parallel form as output, said drift compensation being ensured by the intermediary of an output window,
- a first shift register for checking the position of observation window 14,
- a second shift register for checking the position of output window 18,
- a third shift register for checking the loading and unloading of pipelines 16, and
- a control unit 20 which manages the movement of observation and output windows 14, 18 as a function of the information collected on the position of the transitions in pipelines 16 and as a function of the position of observation window 14.
Dependencies are inferred from the claim text.