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US 6,549,596 B1Granted
Fully digital phase aligner
AssigneeSTMicroelectronics S.r.l.
InventorsFranceso Cretti, Nuccio Villa
Life of this patent
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Abstract
A fully digital phase aligner includes a control loop acting upon a delay line comprising at least a cascade of delay cells, each cell being individually configurable to produce one of two selectable propagation delays as a function of the logic state of a respective digital control signal. This is done by way of a shift register including a number of latches equal to the number of the cells of the delay line. An output tap of each latch of the shift register controls a respective delay cell of the delay line. A digital state machine in the control loop prevents any undesired oscillations.
Claims32
A phase aligner in the form of an all-digital control loop and comprising:
- a digital delay line having an input coupled to an incoming data stream and outputting a delayed data stream, said digital delay line comprising a plurality of delay cells arranged in at least one cascade with each cell being individually configurable to produce a selectable propagation delay as a function of a logic state of a respective digital control signal;
- a digital phase detector discriminating on a phase lead or lag between a clock signal and the delayed data stream from said digital delay line;
- a digital state machine defining a loop filter coupled to an output of said digital phase detector for checking oscillatory behavior of the control loop;
- a digital delay line control circuit regulating the delay introduced by said digital delay line, said digital delay line control circuit comprising a shift register including a plurality of latches equal to a number of delay cells, each latch having an output tap controlling a respective delay cell;
- and
- a digital output circuit receiving the delayed data stream from said digital delay line and outputting a logic bitstream of information congruent with information content of the incoming data stream.
3 more elements
A phase aligner comprising:
- a delay line having an input coupled to an incoming data stream and outputting a delayed data stream, said delay line comprising a plurality of delay cells arranged in at least one cascade with each cell being individually configurable to produce a selectable propagation delay as a function of a logic state of a respective digital control signal;
- a phase detector discriminating on a phase lead or lag between a clock signal and the delayed data stream from said delay line;
- a state machine defining a loop filter coupled to an output of said phase detector for checking oscillatory behavior;
- a delay line control circuit regulating the delay introduced by said delay line, said delay line control circuit comprising a shift register including a plurality of latches, each latch having an output tap controlling a respective delay cell;
- and
- an output circuit receiving the delayed data stream from said delay line and outputting a logic bitstream of information congruent with information content of the incoming data stream.
3 more elements
A phase alignment circuit comprising:
- a pair of phase aligners functioning in parallel and on different clock edges;
- an elastic buffer receiving outputs of said pair of phase aligners and outputting an aligned logic bitstream;
- a logic arbiter circuit selecting alternatively one or other of said pair of phase aligners whenever a currently selected phase aligner reaches a limit of phase adjustment capability for automatically implementing a n phase shift, thereby expanding a range of compensatable phase drift;
- each phase aligner comprising
- a delay line having an input coupled to an incoming data stream and outputting a delayed data stream, said delay line comprising a plurality of delay cells arranged in at least one cascade with each cell being individually configurable to produce a selectable propagation delay as a function of a logic state of a respective digital control signal, a phase detector discriminating on a phase lead or lag between a clock signal and the delayed data stream from said delay line,
- a state machine defining a loop filter coupled to an output of said phase detector for checking oscillatory behavior,
- a delay line control circuit regulating the delay introduced by said delay line, said delay line control circuit comprising a shift register including a plurality of latches, each latch having an output tap controlling a respective delay cell, and
- an output circuit receiving the delayed data stream from said delay line and outputting a logic bitstream of information congruent with information content of the incoming data stream.
5 more elements
A method for phase alignment comprising the steps of:
- coupling an input of a delay line to an incoming data stream and outputting a delayed data stream, the delay line comprising a plurality of delay cells arranged in at least one cascade with each cell being individually configurable to produce a selectable propagation delay as a function of a logic state of a respective digital control signal;
- discriminating on a phase lead or lag between a clock signal and the delayed data stream from the delay line using a phase detector;
- checking oscillatory behavior using a state machine defining a loop filter coupled to an output of the phase detector;
- regulating delay introduced by the delay line using a shift register including a plurality of latches with each latch having an output tap controlling a respective delay cell;
- and
- receiving the delayed data stream from the delay line and outputting a logic bitstream of information congruent with information content of the incoming data stream.
3 more elements
Dependencies are inferred from the claim text.