Interface apparatus for interfacing data to a plurality of different clock domains

Interface apparatus for interfacing data to a plurality of different clock domains where the clock signals in the different domains are phase locked together and respective clock signals have different frequencies, and the data rate of data to be interfaced is slower than the clock rate of the slowest domain clock, said interface apparatus comprising:

• a plurality of cascade connected first and second latches coupled between respective clock domains, one of said first and second latches being a clocked Data Latch and the other of said first and second latches being a clocked and Enabled Data Latch, respective clocked Data Latches having a data and a clock input connection and a data output connection, and respective clocked and Enabled Data Latches each having a clock and an enable input connection and a data output connection;
• a timing generator having output connections providing respective domain clock signals, wherein a domain clock signal of a domain providing a data signal is applied to the clock input connection of the first latch of a respective cascade connected set of latches and a domain clock signal of a domain receiving said data signal is applied to the second latch of a respective cascade connected set of latches;
• said timing generator providing a common Enable Signal phase locked to said domain clock signals, said common Enable Signal being applied to the enable input connection of said other of said first and second latches of each set of cascade connected latches.