Back to results
US 6,549,485 B2Granted
Control and timing structure for a memory
AssigneeSTMicroelectronics S.r.l.
InventorLuigi Pascucci
Life of this patent
Estimating the term…
Loading patent…
Loading patent…
AssigneeSTMicroelectronics S.r.l.
InventorLuigi Pascucci
Estimating the term…
A timing and control structure for a memory, including the timing and control structure includes a first circuit that can recognize, on the basis of control signals supplied to the memory from the exterior, whether a random-access reading is to be executed, the control signals including a first control signal indicative of the presence of an address supplied to the memory from the exterior, and a second control signal that, upon switching edges of a first type, supplies to the control and timing structure a time base for the execution of the random-access readings and, upon switching edges of a second type, supplies a time base for the execution of the sequential readings, a second circuit controlled by the first circuit and upon a random-access reading, generates a first synchronism signal in response to a transition of the first type in the second control signal, a third circuit sensitive to transitions of the second type in the second control signal and which can generate a second synchronism signal upon transitions of the second type, and a fourth circuit controlled by the first circuit to supply a stimulus signal to a timing circuit of the memory, the stimulus signal corresponding to the first synchronism signal for a random-access reading, or to the second synchronism signal for a sequential reading.
A timing and control structure for a memory that has a pair of memory banks each of which is associated with respective circuits for selecting the memory locations of the bank and respective circuits for reading the contents of the locations selected, and an internal addressing structure for executing random-access readings by accessing locations corresponding to addresses supplied to the memory from the exterior, and sequential readings by accessing, in sequence, starting from an origin memory location the address of which is supplied to the memory from the exterior, memory locations succeeding the origin location and belonging to one and to the other of the memory banks, the timing and control structure comprising:
A semiconductor memory comprising a pair of memory banks each of which is associated with respective circuits for selecting memory locations of the bank and respective circuits for reading the contents of the locations selected, and an internal addressing structure for executing random-access readings by accessing locations corresponding to addresses supplied to the memory from the exterior, and sequential readings by accessing, in sequence, starting from an origin memory location the address of which is supplied to the memory from the exterior, memory locations succeeding the origin location and belonging to one and to the other of the memory banks, alternately, and a timing and control structure comprising:
A timing and control structure for a memory having first and second memory banks and configured to read the first and second memory banks by random access readings in response to external addresses, and to read the first and second memory banks in sequential readings by accessing, in sequence, memory locations supplied to the memory from external addresses beginning from an original memory location and succeeding sequentially to one and then to the other of the first and second memory banks alternatingly, the timing and control structure comprising:
A timing and control structure for a memory having first and second memory banks and configured to read the first and second memory banks by random access readings in response to external addresses, and to read the first and second memory banks in sequential readings by accessing, in sequence, memory locations supplied to the memory from external addresses beginning from an original memory location and succeeding sequentially to one and then to the other of the first and second memory banks alternatingly, the timing and control structure comprising:
A timing and control structure for a memory having first and second memory banks and configured to read the first and second memory banks by random access readings in response to external addresses, and to read the first and second memory banks in sequential readings by accessing, in sequence, memory locations supplied to the memory from external addresses beginning from an original memory location and succeeding sequentially to one and then to the other of the first and second memory banks alternatingly, the timing and control structure comprising:
Dependencies are inferred from the claim text.