RAM having dynamically switchable access modes

A method for operating DRAM memory having row decoder blacks and bitline access circuit blocks comprising:

• a) providing a page mode signal for switching the DRAM memory between a long page access mode and a short page access mode;
• b) providing a differential access mode signal for switching the DRAM memory between single cell per bit and dual cell per bit modes;
• c) decoding the page mode signal and a first row address signal for generating column control signals, the column control signals enabling between one half and all of the bitline access circuit blocks;
• d) decoding the differential access mode signal and a second row address signal for generating row decoder control signals;
• and,
• e) decoding the column control signals and the row decoder control signals for generating predecoded row address signals, the predecoded row address signals enabling activation of at least one wordline in each row decoder block corresponding to the enabled bitline access circuit blocks.

A master row decoder circuit for enabling bitline access circuit blocks and row decoder blocks comprising:

• address input buffers for generating first complementary row address signals and second complementary row address signals in response to first and second address signals respectively;
• mode input buffers for generating a page mode signal and a differential access mode signal in response to first and second mode signals respectively;
• column enabling logic for decoding the first complementary row address signals and the page mode signal for generating column control signals, the column control signals selectively enabling one half of the bitline access circuit blocks when the page mode signal is at a logic level corresponding to a short page access mode, and for enabling all of the bitline access circuit blocks when the page mode signal is at a logic level corresponding to a long page access mode;
• row enabling logic for decoding the second complementary row address signals and the differential access mode signal for generating row decoder control signals, the row decoder control signals activating one wordline driver in each row decoder block when the differential access mode signal is at a logic level corresponding to a single cell per bit mode, and two wordline drivers in each row decoder block when the differential access mode signal is at a logic level corresponding to a dual cell per bit mode;
• and,
• a row predecoder for decoding the column control signals and the row decoder control signals for generating predecoded row address signals, the predecoded row address signals selectively enabling one half of the row decoder blocks when the page mode signal is at a logic level corresponding to the short page access mode, and all the row decoder blocks when the page mode signal is at a logic level corresponding to the long page access mode.

A master row decoder circuit for enabling bitline access circuit blocks and row decoder blocks comprising:

• an address input buffer for generating complementary row address signals in response to a row address;
• a mode input buffer for generating a page mode signal in response to a mode signal, the mode signal dynamically switching the master row decoder operation between a short page access mode and a long page access mode;
• and,
• column enabling logic for decoding the complementary row address signals and the page mode signal for selectively enabling one half of the bitline access circuit blocks and one half of the row decoder blocks when the page mode signal is at a logic level corresponding to the short page access mode, and for enabling all of the bitline access circuit blocks and the row decoder blocks when the page mode signal is at a logic level corresponding to the long page access mode.