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US 6,549,479 B2Granted
Memory device and method having reduced-power self-refresh mode
AssigneeMicron Technology, Inc.
InventorGreg A. Blodgett
Life of this patent
Estimating the term…
Abstract
A dynamic random access memory device uses a gray code counter to generate addresses in a self-refresh operating mode so that only one bit of a row address generated by the counter changes state from one refresh cycle to the next. The row addresses are applied to a row address pre-decoder that coupled pre-decoded row address signals to a memory array in the memory device. The row address pre-decoder is operable to continuously couple at least some of the pre-decoded row address signals to the array from one refresh cycle to the next. As a result, only one a plurality of signal lines coupling the pre-decoded row address signals to the array must change state from one refresh cycle to the next, thereby minimizing the power consumed during the self-refresh mode.
Claims51
A refresh controller, comprising:
- an oscillator generating a periodic signal;
- and
- a gray code counter having a clock input coupled to receive the periodic signal from the oscillator, the counter generating a plurality of bits corresponding to the count of the counter.
A row decoder, comprising:
- a pre-decoder circuit operable to generate pre-decoded row address signals;
- a logic gate coupled to some but less than all of the output terminals of the pre-decoder circuit, the logic gate being opened responsive to a control signal that is active during a predetermined phase of a refresh cycle;
- and
- a biasing switch coupled to an output terminal of each logic gate, each biasing switch being operable to couple the respective logic gate output terminal to a predetermined voltage responsive to the control signal being active.
1 more element
A dynamic random access memory, comprising:
- an array of memory cells divided into a plurality of sub-arrays, the memory cells in each of the sub-arrays being arranged in rows and columns;
- an oscillator generating a periodic signal;
- a gray code counter having a clock input coupled to receive the periodic signal from the oscillator, the counter generating a plurality of bits corresponding to the count of the counter;
- a plurality of row decoders located within the memory sub-arrays, each of the row decoders being operable to decode pre-decoded row address signals and activate corresponding word lines of the sub-array;
- a row address pre-decoder coupled to receive the bits from the counter;
- the row address pre-decoder generating at respective output terminals the pre-decoded row address signals corresponding to respective combinations of the bits from the counter, the pre-decoded row address being coupled through respective signal lines to the row decoders;
- a column address decoder coupled to receive column address signal and to enable respective columns of memory cells in each sub-array;
- a data path coupled between the memory array and a data bus;
- and
- a command decoder operable to receive memory commands from a command bus and to generate control signals corresponding to respective memory commands.
7 more elements
A dynamic random access memory, comprising:
- an array of memory cells divided into a plurality of sub-arrays, the memory cells in each of the sub-arrays being arranged in rows and columns;
- an oscillator generating a periodic signal;
- a counter having a clock input coupled to receive the periodic signal from the oscillator, the counter generating a plurality of bits corresponding to the count of the counter;
- a pre-decoder circuit coupled to receive the bits from the counter and being operable to decode the bits from the counter and generate corresponding pre-decoded row address signals;
- a logic gate coupled to some but less than all of the output terminals of the pre-decoder circuit, the logic gate being opened responsive to a control signal that is active during a predetermined phase of a refresh cycle;
- a biasing switch coupled to an output terminal of each logic gate, each biasing switch being operable to couple the respective logic gate output terminal to a predetermined voltage responsive to the control signal being active;
- a plurality of row decoders located within the memory sub-arrays, each of the row decoders being coupled to receive the pre-decoded row address signals from the pre-decoder circuit and each logic gate, the row decoders being operable to decode the pre-decoded row address signals and activate corresponding word lines of the sub-array;
- a column address decoder coupled to receive column address signal and to enable respective columns of memory cells in each sub-array;
- a data path coupled between the memory array and a data bus;
- and
- a command decoder operable to receive memory commands from a command bus and to generate control signals corresponding to respective memory commands.
8 more elements
A computer system, comprising:
- computer circuitry operable to perform computing functions;
- at least one input device coupled to the computer circuitry;
- at least one output device coupled to the computer circuitry;
- at least one data storage devices coupled to the computer circuitry;
- and
- a dynamic random access memory, comprising
- an array of memory cells divided into a plurality of sub-arrays, the memory cells in each of the sub-arrays being arranged in rows and columns;
- an oscillator generating a periodic signal;
- a gray code counter having a clock input coupled to receive the periodic signal from the oscillator, the counter generating a plurality of bits corresponding to the count of the counter;
- a plurality of row decoders located within the memory sub-arrays, each of the row decoders being operable to decode pre-decoded row address signals and activate corresponding word lines of the sub-array;
- a row address pre-decoder coupled to receive the bits from the counter;
- the row address pre-decoder generating at respective output terminals the pre-decoded row address signals corresponding to respective combinations of the bits from the counter, the pre-decoded row address being coupled through respective signal lines to the row decoders;
- a column address decoder coupled to receive column address signal and to enable respective columns of memory cells in each sub-array;
- a data path coupled between the memory array and a data bus;
- and
- a command decoder operable to receive memory commands from a command bus and to generate control signals corresponding to respective memory commands.
13 more elements
A computer system, comprising:
- computer circuitry operable to perform computing functions;
- at least one input device coupled to the computer circuitry;
- at least one output device coupled to the computer circuitry;
- at least one data storage devices coupled to the computer circuitry;
- and
- a dynamic random access memory, comprising
- an array of memory cells divided into a plurality of sub-arrays, the memory cells in each of the sub-arrays being arranged in rows and columns;
- an oscillator generating a periodic signal;
- a counter having a clock input coupled to receive the periodic signal from the oscillator, the counter generating a plurality of bits corresponding to the count of the counter;
- a pre-decoder circuit coupled to receive the bits from the counter and being operable to decode the bits from the counter and generate corresponding pre-decoded row address signals;
- a logic gate coupled to some but less than all of the output terminals of the pre-decoder circuit, the logic gate being opened responsive to a control signal that is active during a predetermined phase of a refresh cycle;
- a biasing switch coupled to an output terminal of each logic gate, each biasing switch being operable to couple the respective logic gate output terminal to a predetermined voltage responsive to the control signal being active;
- a plurality of row decoders located within the memory sub-arrays, each of the row decoders being coupled to receive the pre-decoded row address signals from the pre-decoder circuit and each logic gate, the row decoders being operable to decode the pre-decoded row address signals and activate corresponding word lines of the sub-array;
- a column address decoder coupled to receive column address signal and to enable respective columns of memory cells in each sub-array;
- a data path coupled between the memory array and a data bus;
- and
- a command decoder operable to receive memory commands from a command bus and to generate control signals corresponding to respective memory commands.
14 more elements
A method of refreshing an array of memory cells in a dynamic random access memory, the method comprising:
- generating combinations of active row address bits, the combinations being generated in a sequence in which only one bit in each combination changes from one combination in the sequence to the next;
- and
- coupling the active row address bits to row decoders located in the array of memory cells.
A method of refreshing an array of memory cells in a dynamic random access memory, the method comprising:
- generating combinations of row address bits, and
- continuously coupling at least some of the row address bits to the row decoders from one refresh cycle to the next.
In a dynamic random access memory having an array of memory cells divided into a plurality of sub-arrays, a method of refreshing the memory cells comprising:
- generating pre-decoded row address signals corresponding to incrementing gray code bits;
- decoding the pre-decoded row address signals;
- and
- activating word lines of the sub-array corresponding to the decoded pre-decoded row address signals.
1 more element
Dependencies are inferred from the claim text.