Scan register circuit for scanning data for determining failure in a semiconductor device
AssigneeFujitsu Limited
InventorMasahito Suzuki
Life of this patent
Estimating the term…
Abstract
Failure determination of a memory is made in sequence based on address information supplied to the memory using a test circuit built inside the memory, and resultant failure determination information output from a comparator circuit and the address information output from an address counter circuit are fetched in sequence and held in a logic scan chain, whereby the logic scan chain which is originally provided for a logic test is efficiently used also for a memory test so as to obtain information concerning one or more failure locations and the number of failures by one BIST test without addition of a complicated circuit configuration.
Claims11
A scan register circuit for scanning data comprising:
- a first selector for selecting one of a first data or a second data;
- a second selector for selecting one output of said first selector or a third data;
- and
- a register for latching the output of said second selector;
- wherein said first selector selects said first data at a test on a logic circuit and selects said second data at a test on a semiconductor memory device.
A scan register circuit for scanning data comprising:
- a first selector for selecting one of a first data or a second data;
- a second selector for selecting one output of said first selector or a third data;
- and
- a register for latching the output of said second selector;
- wherein said second selector selects the output of said first selector at a test mode and selects said third data at a normal mode.
A scan register circuit for scanning a data including a first selector, a second selector and a register, wherein said first selector selects one of a first data or a second data, said second selector selects one output of said first selector or a third data that is inputted from the external of the scan register circuit and the register latches the output of said second selector.
A shift register circuit for shifting a data comprising:
- a plurality of scan register circuits, provided in a matrix, for scanning the data, and each of the scan register circuit comprising:
- a first selector for selecting one of a first data or a second data;
- a second selector for selecting one output of said first selector or a third data;
- and
- a register for latching the output of said second selector;
- wherein said first data is shifted in a first direction when said first data is selected and said second data is shifted in a second direction when said second data is selected.
A shift register circuit for shifting a data comprising:
- a plurality of scan register circuits, provided in a matrix, for scanning the data, and each of the scan register circuit comprising:
- a first selector for selecting one of a first data or a second data;
- a second selector for selecting one output of said first selector or a third data that is inputted from the external of the corresponding scan registers circuit;
- and
- a register for latching the output of said second selector.
Dependencies are inferred from the claim text.