Packet-based integrated circuit dynamic random access memory device incorporating an on-chip row register cache to reduce data access latencies

A packet-based integrated circuit device including an address bus and internal read and write data buses, said device comprising:

• at least one dynamic random access memory bank;
• a row decoder associated with each of said at least one dynamic random memory bank, said row decoder being coupled to receive a row address on said address bus;
• a non-gated row register associated with each of said at least one dynamic random memory bank, said row register for providing at least a portion of a row of data accessed from a selected row of an associated one of said at least one dynamic random memory bank to said internal read data bus in response to a corresponding row address provided by an associated row decoder;
• a column decoder associated with each row register, said column decoder being coupled to receive a column address on said address bus;
• and
• a sense amplifier circuit coupled to said write data bus and associated with each of said at least one dynamic random memory bank and coupled between said at least one dynamic random memory bank and an associated row register, said sense amplifier circuit operative to provide data to be written at a specified location in an associated at least one dynamic random memory bank in response to said row and column addresses.