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US 6,549,471 B1Granted
Adiabatic differential driver
AssigneeMicron Technology, Inc.
InventorBranimir Zivanovic
Life of this patent
Estimating the term…
Abstract
A differential driver circuit includes an output connection equilibration circuit. The equilibration circuit balances the output connection voltages to reduce current consumption when transitioning the driver between data states. Equilibrating the differential driver can reduce the current consumption experienced by prior circuits. In one embodiment, the driver circuit is placed in a tri-state condition while the output connections are electrically shorted together. After the output connection have reduced their voltage differential, or reached an intermediate equal level, the driver circuit(s) are activated.
Claims28
An integrated circuit differential driver comprising:
- first and second driver circuits respectively coupled to first and second output connections;
- and
- equilibration circuitry coupled between the first and second output connections to selectively equalize voltages on the first and second output connections in response to the equilibration circuitry detecting a transition on input signals to the differential driver.
A differential driver circuitry comprising:
- a first driver circuit to provide an output signal on a first output connection in response to a first input signal;
- a second driver circuit to provide an output signal on a second output connection in response to a second input signal;
- tri-state circuitry to selectively place the first and second driver circuits in tri-state;
- and
- an equilibration circuit coupled between the first and second output connections to selectively equalize voltages on the first and second output connections, in response to transitions on signals used to derive the first and second input signals, while the first and second driver circuits are tri-state.
2 more elements
A differential driver circuitry comprising:
- a first driver circuit to provide an output signal on a first output connection, wherein the first driver circuit has first pull-up and pull-down circuits;
- a first logic circuit to control the first pull-up circuit, wherein the first logic circuit provides an output signal in response to a first input signal and a delayed version of the first input signal;
- a second logic circuit to control the first pull-down circuit, wherein the second logic circuit provides an output signal in response to the first input signal and the delayed version of the first input signal;
- a second driver circuit to provide an output signal on a second output connection, wherein the second driver circuit has second pull-up and pull-down circuits;
- a third logic circuit to control the second pull-up circuit, wherein the third logic circuit provides an output signal in response to a second input signal and a delayed version of the second input signal;
- a fourth logic circuit to control the second pull-down circuit wherein the fourth logic circuit provides an output signal in response to the first input signal and the delayed version of the second input signal;
- and
- an equilibration circuit coupled between the first and second output connections to selectively equalize voltages on the first and second output connections while the first and second driver circuits are tri-state, wherein the equilibration circuit provides an output in response to the first input signal and the delayed version of the second input signal.
5 more elements
A memory device comprising:
- a memory array to store data;
- first and second output connections to provide differential output signals;
- and
- a differential driver circuit coupled to the two output connections comprising,
- first and second drivers respectively coupled to the first and second output connections, and
- equilibration circuitry coupled between the first and second output connections to selectively equalize voltages on the first and second output connections in response to transitions of the differential output signals.
3 more elements
A memory device comprising:
- a memory array to store data;
- first and second output connections to provide differential output signals;
- a first driver circuit to provide an output signal on the first output connection in response to a first input signal;
- a second driver circuit to provide an output signal on the second output connection in response to a second input signal;
- tri-state circuitry to selectively place the first and second driver circuits in tri-state;
- and
- an equilibration circuit coupled between the first and second output connections to selectively equalize voltages on the first and second output connections, in response to transitions of the differential output signals, while the first and second driver circuits are tri-state.
4 more elements
A method of operating a driver circuit comprising:
- receiving differential input signals;
- placing the driver circuit in a tri-state in response to the input signals transitioning logic levels;
- and
- performing an equilibration operation on output connections of the driver circuit while the driver circuit is tri-state.
1 more element
A method of operating a driver circuit comprising:
- receiving differential input signals;
- detecting a transition in the input signals;
- placing the driver circuit in a tri-state for a predetermined period of time when the transition is detected;
- and
- activating a transistor coupled between output connections for the predetermined time period to perform an equilibration operation on output connections of the driver circuit.
2 more elements
An electronic system comprising:
- a processor that controls the electronic system;
- and
- a memory device coupled to the processor, the memory device comprising:
- a memory array to store data;
- first and second output connections to provide differential output signals;
- and
- a differential driver circuit coupled to the two output connections comprising:
- first and second drivers respectively coupled to the first and second output connections, and
- equilibration circuitry coupled between the first and second output connections to selectively equalize voltages on the first and second output connections in response to transitions of the differential output signals.
6 more elements
Dependencies are inferred from the claim text.