Non-volatile memory with address descrambling
AssigneeMicron Technology, Inc.
InventorsCliff Zitlaw, Kevin C. Widmer, Frankie Fariborz Roohparvar
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Abstract
A flash memory has been described that can be coupled to an SDRAM controller that performs address scrambling. The flash memory includes a programmable address de-scrambler. The de-scrambler can be programmed to de-scramble primarily row addresses, including bank addresses, to maintain a common erase block location for sequential data. The present invention reduces the possibility of writing contiguous data to multiple erase blocks. The de-scrambler can be implemented as a programmable switch. The switch includes a routing circuit that can be programmed in a non-volatile manner.
Claims24
A non-volatile memory comprising:
- a plurality of external address connections;
- and
- an address de-scrambler circuit coupled to the plurality of external address connections, wherein the address de-scrambler circuit re-routes signals received on the plurality of address input connections to internal address circuitry.
A flash memory comprising:
- an array of non-volatile memory cells arranged in erasable blocks;
- address circuitry to access the array;
- a plurality of external address connections;
- and
- an address de-scrambler circuit coupled to the plurality of external address connections, wherein the address de-scrambler circuit re-routes signals received on the plurality of external address connections to the address circuitry.
A processing system comprising:
- a memory controller to provide scrambled addresses;
- and
- a flash memory coupled to receive the scrambled addresses, the flash memory comprises an address de-scrambler circuit coupled to de-scramble the scrambled addresses.
A synchronous flash memory device comprising:
- an array of non-volatile memory cells arranged in erasable blocks;
- address circuitry to access the array;
- data connections, coupled to the array of non-volatile memory cells, to receive data signals;
- a plurality of external address connections;
- and
- an address de-scrambler circuit coupled to the plurality of external address connections, wherein the address de-scrambler circuit re-routes signals received on the plurality of external address connections to the address circuitry in the erasable blocks of the array.
A method of accessing a flash memory comprising:
- receiving scrambled address signals;
- de-scrambling the address signals;
- and
- accessing the memory using the de-scrambled addresses.
A method of writing to a synchronous memory device comprising:
- receiving scrambled address signals;
- receiving data corresponding to the scrambled address signals;
- de-scrambling the address signals using an internal de-scrambler;
- and
- storing the data in the memory using the de-scrambled addresses.
A method of reading a synchronous memory device comprising:
- receiving scrambled address signals;
- de-scrambling the address signals using an internal de-scrambler;
- and
- reading data stored in the memory using the de-scrambled addresses.
A flash memory comprising:
- an array of non-volatile memory cells arranged in erasable blocks;
- address circuitry to access the array;
- a plurality of external address connections;
- and
- an address de-scrambler circuit having a cross point switch coupled to the plurality of external address connections, wherein the cross point switch re-route signals received on the plurality of external address connections to the address circuitry in response to non-volatile cells in the cross point switch.
A processing system comprising:
- a memory controller to provide scrambled addresses;
- and
- a flash memory coupled to receive the scrambled addresses, the flash memory comprises an address de-scrambler circuit having a cross point switch to de-scramble the scrambled addresses in response to non-volatile cells in the cross point switch.
Dependencies are inferred from the claim text.