Non-volatile memory device with erase address register

A non-volatile memory device comprising:

• an array of non-volatile memory cells arranged in erasable blocks;
• address registers associated with the erasable blocks, where each of the address registers store a start verification address for its associated erasable block;
• and
• an address counter, wherein contents of the address counter can be copied to the address registers, and the start verification address stored in any of the address registers can be copied to the address counter.

A non-volatile flash memory device comprising:

• an array of non-volatile memory cells arranged in erasable blocks, where each erasable block comprises a plurality of sub-blocks;
• a plurality of sub-block start address registers comprising a plurality of bits, where each of the plurality of sub-block start address registers is associated with one of the sub-blocks, each of the sub-block start address registers is configured to store a start address for its associated sub-block;
• and
• a control circuit to verify an erase state of the non-volatile memory cells of the array, wherein the control circuitry during operation begins verification of each sub-block at a memory cell address equal to the sub-block start address by loading the sub-block start address in an address counter.

A non-volatile flash memory device comprising:

• an array of non-volatile memory cells arranged in erasable blocks, where each erasable block comprises a plurality of sub-blocks;
• a plurality of sub-block start address registers, where each of the plurality of sub-block start address registers is associated with one of the sub-blocks, each of the sub-block start address registers is configured to store a start address for its associated sub-block;
• a control circuit to verify an erase state of the non-volatile memory cells of the array, wherein the control circuitry during operation begins verification of each sub-block at a memory cell address equal to the sub-block start address;
• and
• wherein the control circuit during operation copies address data from an address counter to one of the plurality of sub-block start address registers when a programmed memory cell is identified while verifying the erase state of the non-volatile memory cells.

A flash memory device comprising:

• an array of memory cells arranged in erasable blocks, wherein each erasable block comprises a plurality of sub-blocks;
• an address counter to provide addresses of the memory cells;
• a plurality of address registers, where each of the plurality of address registers corresponds to one of the plurality of sub-blocks;
• and
• control circuitry coupled to the address counter and the plurality of address registers to selectively copy contents of the address counter to any of the plurality of address registers, and the control circuitry is coupled to selectively copy contents of any of the plurality of address registers to the address counter.