Using a negative gate erase voltage applied in steps of decreasing amounts to reduce erase time for a non-volatile memory cell with an oxide-nitride-oxide (ONO) structure

A method of performing an erase operation on a non-volatile memory cell which comprises a drain and a source in a substrate, a first oxide layer on the surface of the substrate, a nitride layer on the first oxide layer, a second oxide layer on the nitride layer, and a polysilicon gate layer on the second oxide layer, the method comprising the subsequent steps of:

• (a) applying an initial negative voltage to the gate;
• (b) reading the state of the cell by applying a positive gate voltage and measuring current from the source to drain of the cell to determine if the cell threshold voltage is below a predetermined value;
• (c) applying an additional negative voltage to the gate less than the last subsequently applied gate erase voltage if the threshold of the cell has not been erased below the predetermined value and returning to step (b),
• wherein the non-volatile memory cell is programmed and erased in a plurality of program-erase cycles including a first program-erase cycle and a plurality of program-erase cycles subsequent to the first program-erase cycle, and wherein the steps (a), (b) and (c) are applied during the first program erase cycle, the first program-erase cycle further comprising the step of:
• (d) storing the last subsequently applied negative gate voltage value, and
• wherein in a second program-erase cycle, the cell is reprogrammed and steps for erasing in the second program-erase cycle comprise the steps of:
• (e) applying the stored gate voltage value to the gate of the cell;
• (f) reading the state of the cell by applying a positive gate voltage and measuring current from the source to drain of the cell to determine if the cell threshold voltage is below a predetermined value;
• (g) applying an additional negative voltage to the gate less than the last subsequently applied gate erase voltage if the threshold of the cell has not been erased below the predetermined value and returning to step (f).

A method of performing an erase operation on a non-volatile memory cell which comprises a drain and a source in a substrate, a first oxide layer on the surface of the substrate, a nitride layer on the first oxide layer, a second oxide layer on the nitride layer, and a polysilicon gate layer on the second oxide layer, the method comprising the subsequent steps of:

• (a) applying an initial negative voltage to the gate;
• (b) reading the state of the cell by applying a positive gate voltage and measuring current from the source to drain of the cell to determine if the cell threshold voltage is below a predetermined value;
• (c) applying an additional negative voltage to the gate less than the last subsequently applied gate erase voltage if the threshold of the cell has not been erased below the predetermined value and returning to step (b),
• wherein during application of the initial gate voltage and the additional gate voltage, a positive bias voltage is applied to the drain while the source is grounded.

A method of performing an erase operation on a non-volatile memory cell which comprises a drain and a source in a substrate, a first oxide layer on the surface of the substrate, a nitride layer on the first oxide layer, a second oxide layer on the nitride layer, and a polysilicon gate layer on the second oxide layer, the method comprising the subsequent steps of:

• (a) applying an initial negative voltage to the gate;
• (b) reading the state of the cell by applying a positive gate voltage and measuring current from the source to drain of the cell to determine if the cell threshold voltage is below a predetermined value;
• (c) applying an additional negative voltage to the gate less than the last subsequently applied gate erase voltage if the threshold of the cell has not been erased below the predetermined value and returning to step (b),
• wherein during application of the initial gate voltage and the additional gate voltage, a positive bias voltage is applied to the source while the drain is grounded.