Nonvolatile semiconductor memory well voltage setting circuit without latchup and semiconductor memory device provided with the circuit

A well voltage setting circuit of a nonvolatile semiconductor memory, comprising:

• floating-gate field-effect transistors able to electrically write and erase information, the floating-gate field-effect transistors being each provided with a control gate, a floating gate, a drain and a source, and arranged in rows and columns into a block to form a memory cell array;
• a plurality of row lines each connected to control gates of the floating-gate field-effect transistors in each row;
• a plurality of column lines each connected to drains of the floating-gate field-effect transistors in each column;
• a source line connected commonly to sources of the floating-gate field-effect transistors in the block;
• a first voltage supply circuit for applying a first voltage to a well which constitutes each of channel regions in arrangement of the memory cell array to be erased when an erase pulse is applied to the memory cell array in an erase operation wherein information of the memory cell array is erased on a block basis by channel erase using a Fowler-Nordheim tunneling phenomenon, wherein the first voltage supply circuit is constituted of a P-MOS transistor;
• a second voltage supply circuit for applying a reference voltage to the well when the erase pulse application ends and during write and during read, wherein the second voltage supply circuit is constituted of an N-MOS transistor;
• and
• a control circuit for controlling the second voltage supply circuit, the control circuit being constituted of a level shifter to apply a voltage lower than a power voltage to a gate of the N-MOS transistor in turning on the N-MOS transistor of the second voltage supply circuit when the erase pulse application ends and to apply a voltage higher than the power voltage to the gate of the N-MOS transistor in turning on the N-MOS transistor of the second voltage supply circuit during write and during read.

A well voltage setting circuit of a nonvolatile semiconductor memory, comprising:

• floating-gate field-effect transistors able to electrically write and erase information, the floating-gate field-effect transistors being each provided with a control gate, a floating gate, a drain and a source, and arranged in rows and columns into a block to form a memory cell array;
• a plurality of row lines each connected to control gates of the floating-gate field-effect transistors in each row;
• a plurality of column lines each connected to drains of the floating-gate field-effect transistors in each column;
• a source line connected commonly to sources of the floating-gate field-effect transistors in the block;
• a first voltage supply circuit for applying a first voltage to a well which constitutes each of channel regions in arrangement of the memory cell array to be erased when an erase pulse is applied to the memory cell array in an erase operation wherein information of the memory cell array is erased on a block basis by channel erase using a Fowler-Nordheim tunneling phenomenon;
• a second voltage supply circuit for applying a reference voltage to the well after the erase pulse application and during write and during read;
• and
• a fourth voltage supply circuit whose capacity for supplying the reference voltage to an input power line of the second voltage supply circuit is made smaller than the capacity thereof during write and during read in a shutdown sequence after the erase pulse application.

A well voltage setting circuit of a nonvolatile semiconductor memory, comprising:

• floating-gate field-effect transistors able to electrically write and erase information, the floating-gate field-effect transistors being each provided with a control gate, a floating gate, a drain and a source, and arranged in rows and columns into a block to form a memory cell array;
• a plurality of row lines each connected to control gates of the floating-gate field-effect transistors in each row;
• a plurality of column lines each connected to drains of the floating-gate field-effect transistors in each column;
• a source line connected commonly to sources of the floating-gate field-effect transistors in the block;
• a first voltage supply circuit for applying a first voltage to a well which constitutes each of channel regions in arrangement of the memory cell array to be erased when an erase pulse is applied to the memory cell array in an erase operation wherein information of the memory cell array is erased on a block basis by channel erase using a Fowler-Nordheim tunneling phenomenon;
• a second voltage supply circuit for applying a reference voltage to the well after the erase pulse application and during write and during read;
• an intermediate voltage supply circuit for supplying an intermediate voltage for making the potential of the well once have an intermediate level between a potential when the erase pulse is applied and the reference voltage to an input power line of the second voltage supply circuit after the erase pulse application by the first voltage supply circuit;
• and
• a reference voltage supply circuit for making the potential of the well have the intermediate level by the intermediate voltage supply circuit and thereafter applying the reference voltage to the input power line of the second voltage supply circuit in a shutdown sequence after the erase pulse application.