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US 6,549,463 B2Granted
Fast program to program verify method
AssigneeHalo LSI, Inc.
InventorsSeiki Ogura, Tomoko Ogura, Nori Ogura
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Abstract
In the present invention a new method for program and program verify is described. The threshold voltage of the memory cell is shifted up and then measured with minimal charging and discharging of the bit lines and control gate lines. Bit line to control gate line capacitance is also used to reduce the number of voltage references needed. Program current is reduced by use of a load device coupled to the source diffusion. The result is increased program bandwidth with lower high voltage charge pump current consumption.
Claims7
A method of programming a dual storage site MONOS memory cell, comprising:
- a) biasing a drain diffusion to a first high voltage,
- b) biasing a source diffusion to ground,
- c) biasing a unselected control gate to a second high voltage,
- d) biasing a selected control gate to a third high voltage,
- e) biasing a word gate to a low voltage.
2 more elements
Dependencies are inferred from the claim text.