Non-volatile memory array using gate breakdown structures

An integrated circuit comprising:

• a non-volatile memory cell including a storage structure supported on a substrate, the storage structure having a gate and a substrate region, the substrate region being disposed beneath the gate and within the substrate, the non-volatile memory cell further including an intervening dielectric layer being disposed between the substrate region and the gate;
• means for applying a programming voltage to the storage structure sufficient to form a permanent conductive path between the gate and the substrate region;
• and
• a core of lower voltage logic transistors surrounded by a ring of higher voltage I/O circuitry, the intervening dielectric layer of the storage structure being of a first thickness, each lower voltage logic transistor of the core having a gate dielectric of a second thickness, the first thickness being substantially equal to the second thickness.

A field programmable gate array (FPGA) comprising:

• a substrate;
• a plurality of word lines supported by the substrate;
• a plurality of bit lines supported by the substrate;
• and
• a plurality of memory cells supported by the substrate, each memory cell comprising:
• a low voltage CMOS storage structure having a gate, a gate dielectric, and a substrate region, the memory cell being configured for programming by rupturing the gate dielectric of the low voltage CMOS storage structure;
• and
• a high voltage p-channel transistor having a gate and a pair of source/drain regions, one of the pair of source/drain regions of the p-channel transistor being coupled to the low voltage CMOS storage structure, the other of the pair of source/drain regions of the p-channel transistor being coupled to one of the plurality of bit lines, the gate of the p-channel transistor being coupled to one of the plurality of word lines, wherein the low voltage CMOS storage structure is configured for programming through the p-channel transistor.

A field programmable gate array (FPGA) comprising:

• a core comprising a plurality of word lines, a plurality of bit lines, a plurality of source voltage lines, and an array of memory cells, each memory cell including an access field effect transistor and a low voltage storage structure, the access field effect transistor having a gate that is connected to one of the plurality of word lines, the access field effect transistor having a first source/drain region that is connected to one of the bit lines, the low voltage storage structure having an N-type substrate region and an N-type gate, the access field effect transistor having a second source/drain region that is coupled to the gate of the low voltage storage structure, the substrate region of the low voltage storage structure being coupled to one of the plurality of source voltage lines, the low voltage storage structure having a gate dielectric of a first thickness;
• a ring of high voltage I/O circuitry that includes high voltage field effect transistors, each of the high voltage field effect transistors having a gate dielectric of a second thickness, the second thickness being greater than the first thickness;
• and
• an on-chip charge pump comprising transistors connected as charge pump capacitors, each transistor that is connected as a charge pump capacitor having a gate dielectric of the second thickness, the charge pump generating a programming voltage that programs a selected one of the memory cells by rupturing the gate dielectric of the low voltage storage structure of the selected memory cell such that a conductive path is formed between the N-type gate of the low voltage storage structure and the substrate region of the low voltage storage structure.