Back to results
US 6,549,457 B1Granted
Using multiple status bits per cell for handling power failures during write operations
AssigneeIntel Corporation
InventorsSujaya Srinivasan, David S. Dressler, John C. Rudelic, Richard E. Fackenthal
Life of this patent
Estimating the term…
Abstract
A multi-level cell memory may include at least two status bits. The status bits may be examined to determine whether or not a write operation was successful after a power loss occurs.
Claims26
A method comprising:
- providing at least two status bits per cell for a multi-level memory;
- and
- using said status bits to determine the programming state of the cell after a power loss.
An article comprising a medium storing instructions that enable a processor-based system to:
- provide at least two status bits per cell for a multi-level memory;
- and
- use said status bits to determine the programming state of the cell after a power loss.
A multi-level memory comprising:
- a cell having at least two status bits;
- and
- an interface to determine the programming state of the cell after a power loss using said status bits.
Dependencies are inferred from the claim text.