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US 6,549,451 B2Granted
Memory cell having reduced leakage current
OwnerRaj Kumar Jaininventor
Life of this patent
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Abstract
A memory cell is provided with a first access transistor coupled to a first terminal of the storage transistor and a second access transistor coupled to a second terminal of the storage transistor is disclosed. The gates of the access transistors are coupled to word lines. In the inactive state, the word lines comprise a negative voltage to reduce leakage current from the memory cell.
Claims32
A memory cell comprising:
- first and second access transistors, each with a gate and first and second terminals;
- first and second bit lines, the first bit line coupled to the first terminal of the first access transistor and the second bit line coupled to the first terminal of the second transistor;
- first and second word lines, the first word line coupled to the first access transistor and the second word line coupled to the second access transistor;
- a storage transistor having a gate and first and second terminals, the first and second terminals respectively coupled to the second terminals of the first and second access transistors;
- and
- wherein the first and second word lines comprise a negative voltage in an inactive state.
3 more elements
A memory cell comprising:
- first and second access transistors, each with a gate and first and second terminals;
- first and second bit lines, the first bit line coupled to the first terminal of the first access transistor and the second bit line coupled to the first terminal of the second transistor;
- first and second word lines, the first word line coupled to the first access transistor and the second word line coupled to the second access transistor;
- a storage transistor having a gate and first and second terminals, the first and second terminals respectively coupled to the second terminals of the first and second access transistors;
- and
- wherein the first and second word lines comprise a negative voltage in an inactive state and a voltage greater than VDD in an active state.
3 more elements
A memory cell comprising:
- first and second access transistors, each with a gate and first and second terminals;
- first and second bit lines, the first bit line coupled to the first terminal of the first access transistor and the second bit line coupled to the first terminal of the second transistor;
- first and second word lines, the first word line coupled to the first access transistor and the second word line coupled to the second access transistor;
- a storage transistor having a gate and first and second terminals, the first and second terminals respectively coupled to the second terminals of the first and second access transistors;
- and
- wherein the first and second word lines comprise a negative voltage in an inactive state, wherein the negative voltage is less than 0V to about −0.9 V.
3 more elements
Dependencies are inferred from the claim text.