US 6,549,444 B2 · Memory device with prefetched data ordering distributed in prefetched data path logic, circuit, and method of ordering prefetched data

Abstract

A memory device is adapted for prefetching data. The memory device has a memory cell array, with local sense amplifiers for receiving data bits prefetched from the memory cell array. The memory device also includes a serializer, and data paths that connect the local sense amplifiers to the serializer. Crossover connections are interposed between stages of the data paths. These transfer data bits between the data paths. Preferably they do that as part of being gates between the stages, which are in turn controlled by a clock. This way ordering is distributed within the data paths, and thus does not limit how fast the clock may become. In addition, the space used remains at a fundamental minimum.

Claims25

Dependent claims

A memory device comprising:

a memory cell array for storing data;
a plurality of local sense amplifiers for receiving data bits prefetched from the memory cell array;
a serializer;
and
a plurality of data paths for guiding the received data bits from respective ones of the local sense amplifiers to the serializer, each of the data paths having a plurality of stages arranged in sequential order prior to the serializer,
wherein a certain stage has a continuing path coupled to a next stage of the same data path, and a transfer path coupled to a next stage of another data path,
each of the plural sequentially ordered stages receiving a clock signal common thereto for sequentially selecting at the plural successive stages between the continuing and the transfer data paths.

4 more elements

A memory device comprising:

a memory cell array for storing data;
a plurality of local sense amplifiers in the memory cell array for receiving data bits prefetched from the memory cell array;
a serializer;
a plurality of data paths receiving prefetched data bits from one of the local sense amplifiers respectively, and outputting the prefetched data bits to the serializer, each data path having a plurality of stages;
and
sequentially arranged plural crossover connections between the local sense amplifiers and the serializer, the plural crossover connections receiving a common clock signal that determines the sequential timing of the plural crossover connections, wherein
a first one of the crossover connections between a first stage in a first one of the data paths and a second stage in a second one of the data paths is adapted to transfer, responsive to a first ordering signal and the common clock signal, a first bit from the first stage in the first data path to one of a second stage in the first data path and to the second stage in the second data path, and a second bit from a first stage in the second data path to one of the second stage in the second data path and to the second stage in the first data path, and
a second one of the crossover connections between the second stage of the first data path and a third stage in a third one of the data paths is adapted to transfer, responsive to a second ordering signal and the common clock signal, a data bit from the second stage in the first data path to one of a third stage in the first data path and to a third stage in the third data path.

5 more elements

A data ordering method comprising:

prefetching a plurality of data bits from a memory array cell onto a plurality of local sense amplifiers;
receiving the data bits in a plurality of respective paths;
receiving a first ordering signal and a clock signal at a first crossover connection;
determining a first data exchanging in a first stage responsive to the first ordering signal, the first data exchanging being whether to transfer a first data bit from a first one of the paths to a second stage of a second one of the paths or to a second stage of the first data path, and a second data bit from the second path to the second stage of the first path or to the second stage of the second data path, said first data exchanging being synchronous with the clock signal;
receiving a second ordering signal and a clock signal at a second crossover connection;
determining a second data exchanging in the second stage responsive to the second ordering signal, the second data exchanging being whether to transfer the data bit transferred to the second stage in the first data path to a third stage of the first data path or to a third stage of a third one of the paths, and the data bit transferred to the second stage in the second data path to a third stage of the second path or to a third stage of a fourth one of the data path, said second data exchanging being synchronous with the clock signal but later in time than the first data exchanging;
and
then receiving the data bits in a serializer.

5 more elements

Dependencies are inferred from the claim text.

Facts

Application

09/834,493Filed 12 Apr 2001

Published

US 2002/0149960 A117 Oct 2002

Granted

15 Apr 2003

Term ends

Not estimatedThe source records don’t support an estimate.

Classification6 codes

G11C 7/106
Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits: data output latches
G11C 7/1006
Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers: data managing, e.g. manipulating data before…
G11C 7/1039
Read-write modes for single port memories, i.e. having either a random port or a serial port: using pipelining techniques, i.e. using latches…
G11C 7/1051
Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers: data output circuits, e.g. read-out amplifiers,…

Memory device with prefetched data ordering distributed in prefetched data path logic, circuit, and method of ordering prefetched data

Life of this patent

Memory device with prefetched data ordering distributed in prefetched data path logic, circuit, and method of ordering prefetched data

Life of this patent

Abstract

Claims25