Multilayer capacitor

A monolithic capacitor, comprising:

• a capacitor body having first and second opposed, generally parallel, planar surfaces;
• m pairs of first and second generally planar internal electrodes located in said capacitor body and extending generally parallel to said first and second planar surfaces, each said pair of internal electrodes being separated by a respective dielectric layer to define a respective capacitive unit, m being a positive integer greater than or equal to one;
• n first external electrodes located on said first planar surface of said capacitor body, n being an integer greater than or equal to 1;
• p second external electrodes located on said first planar surface of said capacitor body, p being an integer greater than or equal to 1;
• n first connection portions operable to electrically connect said first internal electrodes to each other and to a respective one of said first external electrodes, each of said first connection portions being electrically insulated from said second internal electrodes;
• p second connection portions operable to electrically connect said second internal electrodes to each other and to a respective one of said second external electrodes, each of said second connection portions being electrically insulated from said first internal electrodes;
• wherein said first and second connection portions are distributed substantially in a line, only at the periphery of the first and second internal electrodes.

A microprocessor circuit, comprising:

• a microprocessor;
• and
• a monolithic capacitor, comprising:
• a capacitor body having first and second opposed, generally parallel, planar surfaces;
• m pairs of first and second generally planar internal electrodes located in said capacitor body and extending generally parallel to said first and second planar surfaces, each said pair of internal electrodes being separated by a respective dielectric layer to define a respective capacitive unit, m being a positive integer greater than or equal to one;
• n first external electrodes located on said first planar surface of said capacitor body, n being an integer greater than or equal to 1;
• p second external electrodes located on said first planar surface of said capacitor body, p being an integer greater than or equal to 1;
• n first connection portions operable to electrically connect said first internal electrodes to each other and to a respective one of said first external electrodes, each of said first connection portions being electrically insulated from said second internal electrodes;
• p second connection portions operable to electrically connect said second internal electrodes to each other and to a respective one of said second external electrodes, each of said second connection portions being electrically insulated from said first internal electrodes;
• wherein the monolithic capacitor is connected as a decoupling capacitor for said microprocessor.

A high frequency circuit comprising:

• an active element comprising a plurality of terminals,
• a monolithic capacitor connected to at least one of said terminals comprising:
• a capacitor body having first and second opposed, generally parallel, planar surfaces;
• m pairs of first and second generally planar internal electrodes located in said capacitor body and extending generally parallel to said first and second planar surfaces, each said pair of internal electrodes being separated by a respective dielectric layer to define a respective capacitive unit, m being a positive integer greater than or equal to one;
• n first external electrodes located on said first planar surface of said capacitor body, n being an integer greater than or equal to 1;
• p second external electrodes located on said first planar surface of said capacitor body, p being an integer greater than or equal to 1;
• n first connection portions operable to electrically connect said first internal electrodes to each other and to a respective one of said first external electrodes, each of said first connection portions being electrically insulated from said second internal electrodes;
• p second connection portions operable to electrically connect said second internal electrodes to each other and to a respective one of said second external electrodes, each of said second connection portions being electrically insulated from said first internal electrodes.

A high frequency circuit comprising:

• an active element comprising a plurality of terminals and
• a monolithic capacitor connected to at least one of said terminals comprising:
• a capacitor body having first and second opposed, generally parallel, planar surfaces;
• m pairs of first and second generally planar internal electrodes located in said capacitor body and extending generally parallel to said first and second planar surfaces, each said pair of internal electrodes being separated by a respective dielectric layer to define a respective capacitive unit, m being a positive integer greater than or equal to one;
• n first external electrodes located on said first planar surface of said capacitor body, n being an integer greater than or equal to 1;
• p second external electrodes located on said first planar surface of said capacitor body, p being an integer greater than or equal to 1;
• n first connection portions operable to electrically connect said first internal electrodes to each other and to a respective one of said first external electrodes, each of said first connection portions being electrically insulated from said second internal electrodes;
• p second connection portions operable to electrically connect said second internal electrodes to each other and to a respective one of said second external electrodes, each of said second connection portions being electrically insulated from said first internal electrodes;
• wherein said monolithic capacitor is connected for bypassing high-frequency signals from said at least one terminal to ground.

A wiring substrate having a plurality of conductors, and a monolithic capacitor mounted on said wiring substrate and connected to at least one of said conductors, said monolithic capacitor comprising:

• a capacitor body having first and second opposed, generally parallel, planar surfaces;
• m pairs of first and second generally planar internal electrodes located in said capacitor body and extending generally parallel to said first and second planar surfaces, each said pair of internal electrodes being separated by a respective dielectric layer to define a respective capacitive unit, m being a positive integer greater than or equal to one;
• n first external electrodes located on said first planar surface of said capacitor body, n being an integer greater than or equal to 1;
• p second external electrodes located on said first planar surface of said capacitor body, p being an integer greater than or equal to 1;
• n first connection portions operable to electrically connect said first internal electrodes to each other and to a respective one of said first external electrodes, each of said first connection portions being electrically insulated from said second internal electrodes;
• p second connection portions operable to electrically connect said second internal electrodes to each other and to a respective one of said second external electrodes, each of said second connection portions being electrically insulated from said first internal electrodes.

A wiring substrate comprising a plurality of conductors, and a monolithic capacitor mounted on said wiring substrate and connected to at least one of said conductors, said monolithic capacitor comprising:

• a capacitor body having first and second opposed, generally parallel, planar surfaces;
• m pairs of first and second generally planar internal electrodes located in said capacitor body and extending generally parallel to said first and second planar surfaces, each said pair of internal electrodes being separated by a respective dielectric layer to define a respective capacitive unit, m being a positive integer greater than or equal to one;
• n first external electrodes located on said first planar surface of said capacitor body, n being an integer greater than or equal to 1;
• p second external electrodes located on said first planar surface of said capacitor body, p being an integer greater than or equal to 1;
• n first connection portions operable to electrically connect said first internal electrodes to each other and to a respective one of said first external electrodes, each of said first connection portions being electrically insulated from said second internal electrodes;
• p second connection portions operable to electrically connect said second internal electrodes to each other and to a respective one of said second external electrodes, each of said second connection portions being electrically insulated from said first internal electrodes;
• said monolithic capacitor being mounted to said substrate and connected to said conductors by bump-connection between said conductors and said external terminal electrodes.