Selectable input pole compensation for a disk drive read head
AssigneeTexas Instruments Incorporated
InventorEchere Iroaga
Life of this patent
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Abstract
A selectively adjustable impedance boosting circuit for a magneto-resistive head in a disk drive to compensate a frequency pole by introducing a zero in proportion to the resistance of the magneto-resistive element and with selectable circuit parameters to further adjust the pole compensation. The invention includes selectively adjusting the sensitivity of the pole compensation to changes in the resistance of the head, selectively adjusting the peak compensation, and adjusting the frequency of the compensating zero.
Claims14
A selectively adjustable impedance boosting circuit, comprising:
- a gain stage;
- a magneto-resistive element coupled to the gain stage;
- a variable impedance load circuit coupled in parallel with the gain stage, the variable impedance load circuit operable to adjust the impedance of the boosting circuit in proportion to the resistance of the magneto-resistive element;
- and
- an impedance-controlling circuit element in the variable impedance load with a selectable factor to provide a further selectable adjustment to the frequency response of the variable impedance load circuit.
A disk drive-comprising:
- a read head operable to interface with a storage device;
- and
- a preamplifier circuit coupled to the read head, the preamplifier circuit including an selectively adjustable impedance boosting circuit, comprising:
- a gain stage;
- a magneto-resistive element coupled to the gain stage;
- a variable impedance load circuit coupled in parallel with the, gain stage, the variable impedance load circuit operable to adjust the impedance of the boosting circuit in proportion to the resistance of the magneto-resistive element;
- and
- an impedance-controlling circuit element in the variable impedance load with a selectable factor to provide a further selectable adjustment to the frequency response of the variable impedance load circuit.
A method of increasing the bandwidth of a differential amplifier, comprising:
- approximating a zero in the frequency response of the differential amplifier near the frequency of a pole caused by lead inductance of a magneto-resistive element coupled between the emitters of a differential pair of gain stage transistors;
- determining an actual value of the resistance of the magneto-resistive element;
- selecting a circuit parameter through a pre-amp status register;
- and
- adjusting the impedance of a variable impedance load in proportion to the actual value of the resistance of the magneto-resistive element and adjusting the impedance of the variable impedance load based on the selected circuit parameter, the variable impedance load coupled in parallel with at least a portion of a collector load of the differential amplifier.
Dependencies are inferred from the claim text.