Single substrate camera device with CMOS image sensor

A single chip camera device, comprising:

• a substrate, having integrated thereon an image acquisition portion and a control portion, both of which are formed using a logic family that is compatible with CMOS;
• said image acquisition portion integrated in said substrate including an array of active pixel type photoreceptors, where each element of the array includes both a photoreceptor and a readout amplifier integrated within the same substrate as the photoreceptor;
• said control portion integrated in said substrate including a signal controlling device, controlling said photoreceptors to output their signals,
• said control portion also including, integrated in said substrate, a timing circuit integrated within the same substrate that houses the array of photoreceptors, controlling a timing of operation of said array of photoreceptors, wherein said array of photoreceptors are controlled to output an entire row of said photoreceptors substantially simultaneously;
• and
• a plurality of double sampling charge storage elements integrated on said substrate;
• one for each of said columns.

A single chip camera device, comprising:

• a substrate, having integrated thereon an image acquisition portion and a control portion, both of which are formed using a logic family that is compatible with CMOS;
• said image acquisition portion integrated in said substrate including an array of active pixel type photoreceptors, where each element of the array includes both a photoreceptor and a readout amplifier integrated within the same substrate as the photoreceptor;
• said control portion integrated in said substrate including a signal controlling device, controlling said photoreceptors to output their signals,
• said control portion also including, integrated in said substrate, a timing circuit integrated within the same substrate that houses the array of photoreceptors, controlling a timing of operation of said array of photoreceptors, wherein said signal controlling device includes a column selector allowing selection of a desired colum for read out, and a row selector which allows selection of a desired row fro readout.

A single chip camera device, comprising:

• a substrate, having integrated thereon an image acquisition portion and a control portion, both of which are formed using a logic family that is compatible with CMOS;
• said image acquisition portion integrated in said substrate including an array of photoreceptors;
• said control portion integrated in said substrate including a signal controlling device, controlling said photoreceptors to output their signals, in a way such that at least a plurality of said photoreceptors output their signals at substantially the same time,
• said control portion also including, integrated in said substrate, a timing circuit integrated within the same substrate that houses the array of photoreceptors, controlling a timing of operation of said array of photoreceptors,
• wherein said signal controlling device includes a column selector allowing selection of a desired column for read out, and a row selector which allows selection of a desired row for readout,
• wherein said row selector includes a latch element, storing a value for a row to be selected, and a counter, allowing incrementing of said value to read a next consecutive row, said latch element and said counter both being integrated on said substrate.

A single chip camera device, comprising:

• a substrate, having integrated thereon an image acquisition portion and a control portion, both of which are formed using a logic family that is compatible with CMOS;
• said image acquisition portion integrated in said substrate including an array of photoreceptors;
• said control portion integrated in said substrate including a signal controlling device, controlling said photoreceptors to output their signals, in a way such that at least a plurality of said photoreeptors output their signals at substantially the same time,
• said control portion also including, integrated in said substrate, a timing circuit integrated within the same substrate that houses the array of photoreceptors, controlling a timing of operation of said array of photoreceptors, wherein said signal controlling device includes a column selector allowing selection of a desired column for read out, and a row selector which allows selection of a desired row for readout, wherein said colum selector includes presettable start and stop column decoder counters, which are preset to start and stop at any desired value.

A single chip camera device, comprising:

• a substrate, having integrated thereon an image acquisition portion and a control portion, both of which are formed using a logic family that is compatible with CMOS;
• said image acquisition portion integrated in said substrate including an array of photoreceptors;
• said control portion integrated in said substrate including a signal controlling device, controlling said photoreceptors to output their signals, in a way such that at least a plurality of said photoreceptors output their signals at substantially the same time,
• said control portion also including, integrated in said substrate, a timing circuit integrated within the same substrate that houses the array of photoreceptors, controlling a timing of operation of said array of photoreceptors, further comprising a mode selector device, selecting a mode of operation of said chip,
• wherein said photoreceptors are either photogates or photodiodes, and said mode selector device selects a first mode of operation for operation with photogates, and second mode of operation, different that said first mode of operation, for operation with photodiodes.

A single chip camera device, comprising:

• a substrate, having integrated thereon an image acquisition portion and a control portion, both of which are formed using a logic family that is compatible with CMOS;
• said image acquisition portion integrated in said substrate including an array of photoreceptors;
• said control portion integrated in said substrate including a signal controlling device, controlling said photoreceptors to output their signals, in a way such that at least a plurality of said photoreceptors output their signals at substantially the same time,
• said control portion also including, integrated in said substrate, a timing circuit integrated within the same substrate that houses the array of photoreceptors, controlling a timing of operation of said array of photoreceptors, and
• further comprising a correlated double sampling circuit.

A single chip camera device, comprising:

• a substrate, having integrated thereon an image acquisition portion and a control portion, both of which are formed using a logic family that is compatible with CMOS;
• said image acquisition portion integrated in said substrate including an array of photoreceptors;
• said control portion integrated in said substrate including a signal controlling device, controlling said photoreceptors to output their signals, in a way such that at least a plurality of said photoreceptors output their signals at substantially the same time,
• said control portion also including, integrated in said substrate, a timing circuit integrated within the same substrate that houses the array of photoreceptors, controlling a timing of operation of said array of photoreceptors,
• wherein said timing circuit controls readout from said chip in a correlated double sampling mode.

A single chip camera device, comprising:

• a substrate, having integrated thereon an image acquisition portion and a control portion, both of which are formed using a logic family that is compatible with CMOS;
• said image acquisition portion integrated in said substrate including an array of photoreceptors;
• said control portion integrated in said substrate including a signal controlling device, controlling said photoreceptors to output their signals, in a way such that a least a plurality of said photoreceptors output their signals at substantially the same time,
• said control portion also including, integrated in said substrate, a timing circuit integrated within the same substrate that houses the array of photoreceptors, controlling a timing of operation of said array of photoreceptors,
• wherein said timing circuit allows changing an integration time for said array of photoreceptors.

A single chip camera device, comprising:

• a substrate, having integrated thereon an image acquisition portion and a control portion, both of which are formed using a logic family that is compatible with CMOS;
• said image acquisition portion integrated in said substrate including an array of photoreceptors;
• said control portion integrated in said substrate including a signal controlling device, controlling said photoreceptors to output their signals, in a way such that at least a plurality of said photoreceptors output their signals at substantially the same time,
• said control portion also including, integrated in said substrate, a timing circuit integrated within the same substrate that houses the array of photoreceptors, controlling a timing of operation of said array of photoreceptors, and
• further comprising fixed pattern noise reduction circuits, on said substrate.

A single chip camera device, comprising:

• a substrate, having integrated thereon an image acquisition portion and a control portion, both of which are formed using a logic family that is compatible with CMOS;
• said image acquisition portion integrated in said substrate including an array of photoreceptors;
• said control portion integrated in said substrate including a signal controlling device, controlling said photoreceptors to output their signals, in a way such that at least a plurality of said photoreceptors output their signals at substantially the same time,
• said control portion also including, integrated in said substrate, a timing circuit integrated within the same substrate that houses the array of photoreceptors, controlling a timing of operation of said array of photoreceptors, further comprising a noise reduction circuit,
• wherein said timing circuit times an operation of said noise reduction circuit to occur during a time of the video signal which is not being displayed.

A single chip camera device, comprising:

• a substrate, having integrated thereon an image acquisition portion and a control portion, both of which are formed using a logic family that is compatible with CMOS;
• said image acquisition portion integrated in said substrate including an array of photoreceptors;
• said control portion integrated in said substrate including a signal controlling device, controlling said photoreceptors to output their signals, in a way such that a least a plurality of said photoreceptors output their signals at substantially the same time,
• said control portion also including, integrated in said substrate, a timing circuit integrated within the same substrate that houses the array of photoreceptors, controlling a timing of operation of said array of photoreceptors, and a noise reduction circuit.

A single chip camera device, comprising:

• a substrate, having integrated thereon an image acquisition portion and a control portion, both of which are formed using a logic family that is compatible with CMOS;
• said image acquisition portion integrated in said substrate including an array of photoreceptors;
• said control portion integrated in said substrate including a signal controlling device, controlling said photoreceptors to output their signals, in a way such that at least a plurality of said photoreceptors output their signals at substantially the same time,
• said control portion also including, integrated in said substrate, a timing circuit integrated within the same substrate that houses the array of photoreceptors, controlling a timing of operation of said array of photoreceptors, further comprising a mode selector device, selecting a mode of operation of said chip,
• wherein said photoreceptors are either photogates or photodiodes, and said mode selector device selects a first mode of operation for operation with photogates, and second mode of operation, different that said first mode of operation, for operation with photodiodes.

A single chip camera device, comprising:

• a substrate, having integrated thereon an image acquisition portion and a control portion, both of which are formed using a logic family that is compatible with CMOS;
• said image acquisition portion integrated in said substrate including an array of photoreceptors;
• said control portion integrated in said substrate including a signal controlling device, controlling said photoreceptors to output their signals, and including a preset buffer, allowing present of at least one of a start address for output or a stop address for output;
• said control portion also including, integrated in said substrate, a timing circuit integrated within the same substrate that houses the array of photoreceptors, controlling a timing of operation of said array of photoreceptors.

A single chip camera device, comprising:

• a substrate, having integrated thereon an image acquisition portion and a control portion, both of which are formed using a logic family that is compatible with CMOS;
• said image acquisition portion integrated in said substrate including an array of photoreceptors;
• said control portion integrated in said substrate including a signal controlling device, controlling said photoreceptors to output their signals, and including a preset buffer, allowing preset of at least one of a start address for output or a stop address for output;
• said control portion also including, integrated in said substrate, a timing circuit integrated within the same substrate that houses the array of photoreceptors, controlling a timing of operation of said array of photoreceptors, wherein said array of photoreceptors includes an active pixel sensor, where each element of the array includes both a photoreceptor and a readout amplifier integrated within the same substrate as the photoreceptor.

A single chip camera device, comprising:

• a substrate, having integrated thereon an image acquisition portion and a control portion, both of which are formed using a logic family that is compatible with CMOS;
• said image acquisition portion integrated in said substrate including an array of photoreceptors;
• said control portion integrated in said substrate including a signal controlling device, controlling said photoreceptors to output their signals, and including a preset buffer, allowing preset of at least one of a start address for output or a stop address for output;
• said control portion also including, integrated in said substrate, a timing circuit integrated within the same substrate that houses the array of photoreceptors, controlling a timing of operation of said array of photoreceptors, and a noise reduction circuit.

A single chip camera device, comprising:

• a substrate, having integrated thereon an image acquisition portion and a control portion, both of which are formed using a logic family that is compatible with CMOS;
• said image acquisition portion integrated in said substrate including an array of photoreceptors;
• said control portion integrated in said substrate including a signal controlling device, controlling said photoreceptors to output their signals, and including a preset buffer, allowing preset of at least one of a start address for output or a stop address for output;
• said control portion also including, integrated in said substrate, a timing circuit integrated within the same substrate that houses the array of photoreceptors, controlling a timing of operation of said array of photoreceptors, and a noise reduction circuit.

A single chip camera device, comprising:

• a substrate, having integrated thereon an image acquisition portion and a control portion, both of which are formed using a logic family that is compatible with CMOS;
• said image acquisition portion integrated in said substrate including an array of photoreceptors;
• said control portion integrated in said substrate including a signal controlling device, controlling said photoreceptors to output their signals,
• said control portion also including, integrated in said substrate, a timing circuit integrated within the same substrate that houses the array of photoreceptors, controlling a timing of operation of said array of photoreceptors in a first mode or in a second mode, depending on a type of photoreceptor being used.

A single chip camera device, comprising:

• a substrate, having integrated thereon an image acquisition portion and a control portion, both of which are formed using a logic family that is compatible with CMOS;
• said image acquisition portion integrated in said substrate including an array of photoreceptors;
• said control portion integrated in said substrate including a signal controlling device, controlling said photoreceptors to output their signals,
• said control portion also including, integrated in said substrate, a timing circuit integrated within the same substrate that houses the array of photoreceptors, controlling a timing of operation of said array of photoreceptors in a first mode or in a second mode, depending on a type of photoreceptor being used, further comprising a noise reduction circuit.

A single chip camera device, comprising:

• a substrate, having integrated thereon an image acquisition portion and a control portion, both of which are formed using a logic family that is compatible with CMOS;
• said image acquisition portion integrated in said substrate including an array of photoreceptors;
• said control portion integrated in said substrate including a signal controlling device, controlling said photoreceptors to output their signals,
• said control portion also including, integrated in said substrate, a timing circuit integrated within the same substrate that houses the array of photoreceptors, controlling a timing of operation of said array of photoreceptors,
• said control portion including common logic elements to control row and address decoders and delay counters.

A single chip camera device, comprising:

• a substrate, having integrated thereon an image acquisition portion and a control portion, both of which are formed using a logic family that is compatible with CMOS;
• said image acquisition portion integrated in said substrate including an array of photoreceptors;
• said control portion integrated in said substrate including a signal controlling device, controlling said photoreceptors to output their signals,
• said control portion also including, integrated in said substrate, a timing circuit integrated within the same substrate that houses the array of photoreceptors, controlling a timing of operation of said array of photoreceptors,
• said control portion including common logic elements to control row and address decoders and delay counters, further comprising a mode selector device, selecting a mode of operation of said chip.

A single chip camera device, comprising:

• a substrate, having integrated thereon an image acquisition portion and a control portion, both of which are formed using a logic family that is compatible with CMOS;
• said image acquisition portion integrated in said substrate including an array of photoreceptors;
• said control portion integrated in said substrate including a signal controlling device, controlling said photoreceptors to output their signals, and including a preset buffer, allowing preset of at least one of a start address for output or a stop address for output;
• said control portion also including, integrated in said substrate, a timing circuit integrated within the same substrate that houses the array of photoreceptors, controlling a timing of operation of said array of photoreceptors, wherein said timing circuit allows changing an integration time for said array of photoreceptors.

A single chip camera device, comprising:

• a substrate, having integrated thereon an image acquisition portion and a control portion, both of which are formed using a logic family that is compatible with CMOS;
• said image acquisition portion integrated in said substrate including an array of photoreceptors arranged in row and columns;
• a charge storage element, associated with each said columns;
• said control portion integrated in said substrate including a signal controlling device, controlling said photoreceptors to output their signals,
• said control portion also including, integrated in said substrate, a timing circuit integrated within the same substrate that houses the array of photoreceptors, controlling a timing of operation of said array of photoreceptors;
• said control portion including common logic elements to control all pixels on a selected row to sample said all pixels onto said charge storage elements substantially simultaneously, further comprising a mode selector device, selecting a mode of operation of said chip.

A single chip camera device, comprising:

• a substrate, having integrated thereon an image acquisition portion and a control portion, both of which are formed using a logic family that is compatible with CMOS;
• said image acquisition portion integrated in said substrate including an array of photoreceptors arranged in rows and columns;
• a charge storage element, associated with each said colum;
• said control portion integrated in said substrate including a signal controlling device, controlling said photoreceptors to output their signals,
• said control portion also including, integrated in said substrate, a timing circuit integrated within the same substrate that houses the array of photoreceptors, controlling a timing of operation of said array of photoreceptors,
• said control portion including common logic elements to control all pixels on a selected row to sample said all pixels onto said charge storage elements substantially simultaneously,
• wherein said photoreceptors are either photogates or photodiodes, and said mode selector device selects a first mode of operation for operation with photogates, and a second mode of operation, different than said first mode of operation, for operation with photodiodes.

A single chip camera device, comprising:

• a substrate, having integrated thereon an image acquisition portion and a control portion, both of which are formed using a logic family that is compatible with CMOS;
• said image acquisition portion integrated in said substrate including an array of photoreceptors;
• said control portion integrated in said substrate including a signal controlling device, controlling said photoreceptors to output their signals, and including a preset buffer, allowing preset of at least one of a start address for output or a stop address for output;
• said control portion also including, integrated in said substrate, a timing circuit integrated within the same substrate that houses the array of photoreceptors, controlling a timing of operation of said array of photoreceptors, wherein said timing circuit allows changing an integration time for said array of photoreceptors.