Integrated test structure and method for verification of microelectronic devices

A test structure adapted to test a microelectronic device, said test structure comprising:

• a sample and hold circuit;
• a sample and hold clock, coupled to the sample and hold circuit;
• a first comparator with a first at least one of an analog reference and a fixed offset representing a first error bound and at least a first input coupled to an output of said microelectronic device;
• and
• a second comparator with a second at least one of an analog reference and a fixed offset representing a second error bound and at least a second input coupled to said output of said microelectronic device;
• said test structure responsive to outputs of said first comparator and said second comparator to generate real time pass/fail indicators.

A test structure for testing a microelectronic device, said test structure comprising:

• (1) a first test structure input;
• (2) a first comparator having a first plus (+) input, a first minus (−) input, a first internal offset and a first digital output, said first plus (+) input coupled to an output of at least one switch, the at least one switch operable to select between at least one of an analog reference, a sample and hold circuit, and a slope polarity, said sample and hold circuit coupled to said first test structure input, said first minus (−) input coupled to at least one of said first test structure input and at least one switch, the at least one switch operable to select between at least one of an analog reference, said sample and hold circuit, and a slope polarity;
• and
• (3) a second comparator having a second plus (+) input, a second minus (−) input, a second internal offset and a second digital output, said second minus (−) input coupled to said output of at least one switch, the at least one switch operable to select between at least one of an analog reference, said sample and hold circuit, and a slope polarity, said sample and hold circuit coupled to said first test structure input, said second plus (+) input coupled to at least one of said first test structure input and at least one switch, the at least one switch operable to select between at least one of an analog reference, said sample and hold circuit, and a slope polarity.