Embedded vertical solenoid inductors for RF high power application
AssigneeRaytheon Company
InventorsJan S. Gallina, Michael Brand
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AssigneeRaytheon Company
InventorsJan S. Gallina, Michael Brand
Estimating the term…
Vertical solenoid inductors have windings or layers which are arranged to minimize interwinding capacitance between adjacent layers. Each layer occupies a surface area, and adjacent layers are arranged to occupy different surface areas, except where necessary to provide electrical connection between adjacent layers. The inductors are high power inductors which have high inductances L and high current capabilities. The inductors of the present invention also have high self resonant frequencies and quality factors, while minimizing component volume.
An electrically conductive inductor comprising:
An embedded solenoid inductor comprising:
Dependencies are inferred from the claim text.
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No related US applications are recorded in the indexed filing history.
Coils: printed circuit coils
Coils; Windings; Conductive connections: sheets; Strips
Details of transformers or inductances, in general: special means for preventing or reducing unwanted electric or magnetic effects, e.g. no-load…
Magnets
Term ended 29 Aug 2016 (estimated)
USPTO file history isn’t available for this patent, so only indexed dates are shown.
1. Field of the Invention
This invention relates generally to inductors, and, more particularly, to a design of inductors for high power, radio frequency applications having an optimal combination of self resonant frequency and quality factor while minimizing component volume.
2. Discussion
FIG. 1 is a plan view of a pyramid solenoid inductor arranged in accordance with the principles of the present invention;
FIG. 2 is an exploded perspective view of the pyramid solenoid inductor of FIG. 1;
FIG. 3 is a side view of the pyramid solenoid inductor of FIG. 1;
FIGS. 1-7 depict a pyramid solenoid inductor 10 arranged in accordance with a first embodiment of the present invention. The pyramid solenoid inductor 10 consists of a series of concentric squares wound around a vertical axis with adjacent squares connected by a via. In this particular embodiment, the pyramid solenoid inductor 10 includes a topmost layer 12 connected to an adjacent layer 14 below layer 12. Layers 12 and 14 are electrically connected using a via 16 which provides electrical interaction between the layers. A third layer 18 is adjacent to layer 14 and is similarly interconnected by a via 20. Similarly, a fourth layer 22 is adjacent to layer 18 and is interconnected by a third via 24. As best shown in FIGS. 2 and 3, the interconnection of layers 12, 14, 18, and 22 results in a pyramid structure. The pyramid structure may be located within the layers of a substrate or may be self supporting.
The pyramid solenoid inductors of FIGS. 1-7 minimize interwinding capacitance because the only area of trace overlap between adjacent turns is at the vias 16, 20, and 24. Thus, the overall parasitic capacitance is equal to the series connection of low value fringe (or edge) capacitance between each layer. By adding additional layers (i.e., inductor turns) the capacitance will decrease and the inductance will increase, resulting in a larger inductance with a potentially higher self-resonant frequency (SRF). The pyramid solenoid inductor of FIGS. 1-7 also minimizes proximity effect because the turns are separated along the axial direction of the pyramid, resulting in a decrease in alternating current (AC) resistance and an increase in quality factor (Q). Further yet, the pyramid solenoid inductor enables variation of the inner-edge spacing (i.e., the spacing viewed along the axial direction) between adjacent traces to minimize surface area, thereby maximizing inductance per volume.
FIGS. 8-14 depict a staggered solenoid inductor 30 arranged in accordance with the principles of a second embodiment of the present invention. In general, the staggered solenoid inductor 30 includes alternating large and small turns wound around the vertical axis with the adjacent turns connected by a via. The staggering of alternating layers significantly reduces interwinding capacitance. The appropriate design and layout of each turn further reduces the capacitance between adjacent layers. The staggered solenoid inductor 30 includes a top layer 32. The top layer 32 electrically interconnects to a second layer 34 adjacent to the top layer 32 by a via 36. The second layer 34 electrically interconnects to a third layer 38 through a via 40. The third layer in turn attaches to a fourth layer 42 using a via 44.