Transconductance amplifier, filter using the transconductance amplifier and tuning circuitry for transconductance amplifier in the filter

A filter provided with a plurality of transconductance amplifiers, each of said transconductance amplifiers including an input stage and an output stage,

• said input stage comprising:
• a differential input circuit for converting a differential voltage signal applied thereto into a differential current signal;
• a first pair of regulated cascode circuits for adjusting output voltages of said differential input circuit depending upon a control voltage applied thereto;
• and
• an input section of a pair of current mirror circuits for mirroring the differential current signal from said differential input circuit,
• said differential input circuit, said first pair of regulated cascode circuits, and said input section of the pair of current mirror circuits being connected in series with each other between a voltage source and a ground,
• said output stage comprising:
• an output section of said pair of current mirror circuits;
• a differential current source circuit;
• a second pair of regulated cascode circuits for keeping output voltages of said current mirror circuit to a first bias voltage applied thereto;
• a third pair of regulated cascode circuits for keeping output voltages of said differential current source circuit to a second bias voltage applied thereto, output terminals of said third pair of regulated cascode circuits being connected to output terminals of said second pair of regulated cascode circuits;
• and
• a pair of amplifier output terminals connected to said output terminals of said second and third pairs of regulated cascode circuits,
• said output section of the pair of current mirror circuits, said second and third pairs of regulated cascode circuits and said differential current source circuit being connected in series with each other between the voltage source and the ground.

A transconductance amplifier tuning circuitry including two reference signal input terminals to which reference frequency signals are input, an RC phase-shifter connected to said two reference signal input terminals and provided with two transconductance amplifiers and two capacitors, a multiplier with input terminals connected to two output terminals of said RC phase-shifter and to said two reference signal input terminals, and an operational amplifier with two differential input terminals connected to two output terminals of said multiplier and with an output terminal connected to control terminals of said transconductance amplifiers,

• said tuning circuitry feedback-controlling gains of said two transconductance amplifiers so that said RC phase-shifter always shifts a phase of the input reference frequency signals by 90 degrees,
• each of said two transconductance amplifiers including an input stage and an output stage,
• said input stage comprising:
• a differential input circuit for converting a differential voltage signal applied thereto into a differential current signal;
• a first pair of regulated cascode circuits for adjusting output voltages of said differential input circuit depending upon a control voltage applied thereto;
• and
• an input section of a pair of current mirror circuits for mirroring the differential current signal from said differential input circuit,
• said differential input circuit, said first pair of regulated cascode circuits, and said input section of the pair of current mirror circuits being connected in series with each other between a voltage source and a ground,
• said output stage comprising:
• an output section of said pair of current mirror circuits;
• a differential current source circuit;
• a second pair of regulated cascode circuits for keeping output voltages of said current mirror circuit to a first bias voltage applied thereto;
• a third pair of regulated cascode circuits for keeping output voltages of said differential current source circuit to a second bias voltage applied thereto, output terminals of said third pair of regulated cascode circuits being connected to output terminals of said second pair of regulated cascode circuits;
• and
• a pair of amplifier output terminals connected to said output terminals of said second and third pairs of regulated cascode circuits,
• said output section of the pair of current mirror circuits, said second and third pairs of regulated cascode circuits and said differential current source circuit being connected in series with each other between the voltage source and the ground.

A transconductance amplifier comprising:

• first and second transistors with gates connected respectively to first and second amplifier input terminals to which a differential voltage is input and with sources connected together to a first voltage source;
• third and fourth transistors with sources connected respectively to drains of said first and second transistors;
• a first operational amplifier with a non-inverting input terminal connected to a control terminal which receives a signal for controlling a conductance Gm, with an inverting input terminal connected to a source of said third transistor and with an output terminal connected to a gate of said third transistor;
• a second operational amplifier with a non-inverting input terminal connected to said control terminal, with an inverting input terminal connected to a source of said fourth transistor and with an output terminal connected to a gate of said fourth transistor;
• fifth and sixth transistors with sources connected together to a second voltage source and with drains and gates connected respectively to drains of said third and fourth transistors;
• seventh and eighth transistors with sources connected together to the second voltage source and with gates connected respectively to the drains and gates of said fifth and sixth transistors;
• ninth and tenth transistors with sources connected respectively to drains of said seventh and eighth transistors;
• a third operational amplifier with a non-inverting input terminal connected to a first bias terminal, with an inverting input terminal connected to a source of said ninth transistor and with an output terminal connected to a gate of said ninth transistor;
• a fourth operational amplifier with a non-inverting input terminal connected to said first bias terminal, with an inverting input terminal connected to a source of said tenth transistor and with an output terminal connected to a gate of said tenth transistor;
• eleventh and twelfth transistors with sources connected together to the first voltage source;
• thirteenth and fourteenth transistors with drains connected respectively to drains of said ninth and tenth transistors and with sources connected respectively to drains of said eleventh and twelfth transistors;
• a fifth operational amplifier with a non-inverting input terminal connected to a second bias terminal, with an inverting input terminal connected to a source of said thirteenth transistor and with an output terminal connected to a gate of said thirteenth transistor;
• a sixth operational amplifier with a non-inverting input terminal connected to said second bias terminal, with an inverting input terminal connected to a source of said fourteenth transistor and with an output terminal connected to a gate of said fourteenth transistor;
• and
• first and second amplifier output terminals connected to the drains of said ninth and thirteenth transistors and the drains of said tenth and fourteenth transistors, respectively.

A filter provided with a plurality of transconductance amplifiers, each of said transconductance amplifiers comprising:

• first and second transistors with gates connected respectively to first and second amplifier input terminals to which a differential voltage is input and with sources connected together to a first voltage source;
• third and fourth transistors with sources connected respectively to drains of said first and second transistors;
• a first operational amplifier with a non-inverting input terminal connected to a control terminal which receives a signal for controlling a conductance Gm, with an inverting input terminal connected to a source of said third transistor and with an output terminal connected to a gate of said third transistor;
• a second operational amplifier with a non-inverting input terminal connected to said control terminal, with an inverting input terminal connected to a source of said fourth transistor and with an output terminal connected to a gate of said fourth transistor;
• fifth and sixth transistors with sources connected together to a second voltage source and with drains and gates connected respectively to drains of said third and fourth transistors;
• seventh and eighth transistors with sources connected together to the second voltage source and with gates connected respectively to the drains and gates of said fifth and sixth transistors;
• ninth and tenth transistors with sources connected respectively to drains of said seventh and eighth transistors;
• a third operational amplifier with a non-inverting input terminal connected to a first bias terminal, with an inverting input terminal connected to a source of said ninth transistor and with an output terminal connected to a gate of said ninth transistor;
• a fourth operational amplifier with a non-inverting input terminal connected to said first bias terminal, with an inverting input terminal connected to a source of said tenth transistor and with an output terminal connected to a gate of said tenth transistor;
• eleventh and twelfth transistors with sources connected together to the first voltage source;
• thirteenth and fourteenth transistors with drains connected respectively to drains of said ninth and tenth transistors and with sources connected respectively to drains of said eleventh and twelfth transistors;
• a fifth operational amplifier with a non-inverting input terminal connected to a second bias terminal, with an inverting input terminal connected to a source of said thirteenth transistor and with an output terminal connected to a gate of said thirteenth transistor;
• a sixth operational amplifier with a non-inverting input terminal connected to said second bias terminal, with an inverting input terminal connected to a source of said fourteenth transistor and with an output terminal connected to a gate of said fourteenth transistor;
• and
• first and second amplifier output terminals connected to the drains of said ninth and thirteenth transistors and the drains of said tenth and fourteenth transistors, respectively.

A transconductance amplifier tuning circuitry including first and second reference signal input terminals for receiving reference frequency signals, a control signal output terminal for outputting a control signal, first and second transconductance amplifiers, first and second capacitors, a mixer circuit and an operational amplifier,

• said first and second reference signal input terminals being connected to first and second input terminals of said first transconductance amplifier,
• said first input terminal of said first transconductance amplifier and a first output terminal of said first transconductance amplifier being connected via said first capacitor, said second input terminal of said first transconductance amplifier and a second output terminal of said first transconductance amplifier being connected via said second capacitor,
• said second output terminal of said first transconductance amplifier being connected to a first output terminal of said second transconductance amplifier, said first output terminal of said first transconductance amplifier being connected to a second output terminal of said second transconductance amplifier,
• a first input terminal of said second transconductance amplifier being connected to said first output terminal of said second transconductance amplifier, a second input terminal of said second transconductance amplifier being connected to said second output terminal of said second transconductance amplifier,
• first two input terminals of said mixer circuit being connected to said first and second reference signal input terminals, second two input terminals of said mixer circuit being connected to said first and second output terminals of said first transconductance amplifier,
• two output terminals of said mixer circuit being connected respectively to two differential input terminals of said operational amplifier,
• an output terminal of said operational amplifier being connected to control terminals of said first and second transconductance amplifiers and to said control signal output terminal,
• an RC phase-shifter being configured by said first and second transconductance amplifiers and said first and second capacitors, said mixer circuit and said operational amplifier to form a feedback loop for controlling gains of said first and second transconductance amplifiers so that said RC phase-shifter always shifts a phase of the input reference frequency signals by 90 degrees,
• each of said first and second transconductance amplifiers comprising:
• first and second transistors with gates connected respectively to first and second amplifier input terminals to which a differential voltage is input and with sources connected together to a first voltage source;
• third and fourth transistors with sources connected respectively to drains of said first and second transistors;
• a first operational amplifier with a non-inverting input terminal connected to a control terminal which receives a signal for controlling a conductance Gm, with an inverting input terminal connected to a source of said third transistor and with an output terminal connected to a gate of said third transistor;
• a second operational amplifier with a non-inverting input terminal connected to said control terminal, with an inverting input terminal connected to a source of said fourth transistor and with an output terminal connected to a gate of said fourth transistor;
• fifth and sixth transistors with sources connected together to a second voltage source and with drains and gates connected respectively to drains of said third and fourth transistors;
• seventh and eighth transistors with sources connected together to the second voltage source and with gates connected respectively to the drains and gates of said fifth and sixth transistors;
• ninth and tenth transistors with sources connected respectively to drains of said seventh and eighth transistors;
• a third operational amplifier with a non-inverting input terminal connected to a first bias terminal, with an inverting input terminal connected to a source of said ninth transistor and with an output terminal connected to a gate of said ninth transistor;
• a fourth operational amplifier with a non-inverting input terminal connected to said first bias terminal, with an inverting input terminal connected to a source of said tenth transistor and with an output terminal connected to a gate of said tenth transistor;
• eleventh and twelfth transistors with sources connected together to the first voltage source;
• thirteenth and fourteenth transistors with drains connected respectively to drains of said ninth and tenth transistors and with sources connected respectively to drains of said eleventh and twelfth transistors;
• a fifth operational amplifier with a non-inverting input terminal connected to a second bias terminal, with an inverting input terminal connected to a source of said thirteenth transistor and with an output terminal connected to a gate of said thirteenth transistor;
• a sixth operational amplifier with a non-inverting input terminal connected to said second bias terminal, with an inverting input terminal connected to a source of said fourteenth transistor and with an output terminal connected to a gate of said fourteenth transistor;
• and
• first and second amplifier output terminals connected to the drains of said ninth and thirteenth transistors and the drains of said tenth and fourteenth transistors, respectively.