Variable delay circuit
AssigneeAdvantest Corporation
InventorToshiyuki Okayasu
Life of this patent
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Abstract
A variable delay circuit comprises: a delay compensation unit, which has a plurality of referential delay units that include different numbers of first variable delay elements, the delay amount of which varies based on a control signal, the delay compensation unit generates each of a plurality of the control signals, which are provided to the first variable delay elements, according to a number of the first variable delay elements; and a delay unit which generates the desired delay amount by controlling a plurality of second variable delay elements, which have a same characteristic with the first variable delay elements, by the plurality of control signals.
Claims14
A variable delay circuit for generating a desired delay amount, comprising:
- a delay compensation unit, which has a plurality of referential delay units that include different numbers of first variable delay elements, the delay amount of which varies based on a control signal, and the delay compensation unit generates each of a plurality of said control signals, which are provided to said first variable delay elements included in each of said plurality of referential delay elements, according to a number of said first variable delay elements included in each of said plurality of referential delay units;
- and
- a delay unit for generating said desired delay amount by controlling a plurality of second variable delay elements, which have a same characteristic with said first variable delay elements, by said plurality of control signals.
A variable delay circuit which generates a desired delay amount for a signal to be output to an output terminal, comprising:
- a variable delay element that has a capacitor having a predetermined capacitance and a time constant control unit, which is serially inserted between said capacitor and said output terminal for changing a time constant of said capacitor, and changes a delay amount according to said time constant;
- and
- a delay unit which generates said desired delay amount by selecting said variable delay elements based on said desired delay amount.
A delay signal generating method for generating a delay signal, which is obtained by delaying an input signal for a desired time, comprising:
- a step for generating a plurality of clocks by a plurality of referential delay units having different numbers of first variable delay elements, the delay amount of which changes, based on a control signal;
- a step for comparing each of the phases of a plurality of said clocks and a phase of a referential clock;
- a step for correcting each of said control signals corresponding to a plurality of said clocks according to corresponding said numbers of first variable delay elements based on said compared phase;
- a step for controlling each of said delay amounts of said first variable delay elements based on said corrected control signal;
- and
- a step for generating said delay signal, which is obtained by delaying said input signal for said desired time by controlling a plurality of second variable delay elements, which receives said control signal and is controlled based on said control signal and has a same characteristic with that of said first variable delay element, based on said corrected control signal.
A variable delay circuit for generating a desired delay amount, comprising:
- a first delay compensation unit for outputting a first control signal to generate said desired delay amount;
- a second delay compensation unit for outputting a second control signal to generate said desired delay amount;
- and
- a delay unit having a plurality of second variable delay elements for generating said desired delay amount by controlling said plurality of second variable delay elements by said first control signal and said second control signal output from said first delay compensation unit and said second delay compensation unit;
- wherein
- said first delay compensation unit includes:
- a first referential delay unit which has M numbers (M is a natural number) of first variable delay elements, the delay amount of which varies based on said first control signal;
- a first phase comparator that compares a phase of a referential clock having a predetermined period with a phase of a delay clock, which is obtained by delaying said referential clock by said first variable delay elements included in said first referential delay unit;
- and
- a first control signal generating unit which generates said first control signal based on said comparison performed by said first phase comparator and outputs said first control signal to said delay unit and said first referential delay unit according to a number of said first variable delay elements included in said first referential delay unit;
- and
- a second delay compensation unit includes:
- a second referential delay unit that has N numbers (N is a natural number) of first variable delay elements, said N numbers being different to said M numbers, the delay amount of said first variable delay elements varies based on said second control signal;
- and
- a second phase comparator which compares a phase of a referential clock having a predetermined period with a phase of a delay clock, which is obtained by delaying said referential clock by said first variable delay elements included in said second referential delay unit;
- and
- a second control signal generating unit which generates said second control signal based on said comparison performed by said second phase comparator and outputs said second control signal to said delay unit and said second referential delay unit according to a number of said first variable delay elements included in said second referential delay unit.
Dependencies are inferred from the claim text.